Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T24
1	1	Covered	T4,T6,T24

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	493199037	4625	0	0
g_div2.Div2Whole_A	493199037	5383	0	0
g_div4.Div4Stepped_A	245720438	4540	0	0
g_div4.Div4Whole_A	245720438	5112	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493199037	4625	0	0
T2	0	27	0	0
T4	13165	7	0	0
T5	4891	0	0	0
T6	2377	8	0	0
T15	0	5	0	0
T16	0	3	0	0
T17	0	4	0	0
T22	1400	0	0	0
T23	2826	0	0	0
T24	20494	4	0	0
T25	3185	7	0	0
T26	1475	0	0	0
T27	3572	12	0	0
T28	2244	4	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493199037	5383	0	0
T4	13165	7	0	0
T5	4891	0	0	0
T6	2377	11	0	0
T15	0	4	0	0
T16	0	3	0	0
T17	0	5	0	0
T18	0	1	0	0
T22	1400	0	0	0
T23	2826	0	0	0
T24	20494	4	0	0
T25	3185	9	0	0
T26	1475	0	0	0
T27	3572	13	0	0
T28	2244	7	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245720438	4540	0	0
T2	0	22	0	0
T4	6864	7	0	0
T5	2434	0	0	0
T6	1312	7	0	0
T15	0	5	0	0
T16	0	3	0	0
T17	0	4	0	0
T22	667	0	0	0
T23	1387	0	0	0
T24	11061	4	0	0
T25	1673	7	0	0
T26	671	0	0	0
T27	2073	12	0	0
T28	1206	4	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245720438	5112	0	0
T4	6864	7	0	0
T5	2434	0	0	0
T6	1312	7	0	0
T15	0	4	0	0
T16	0	3	0	0
T17	0	5	0	0
T18	0	1	0	0
T22	667	0	0	0
T23	1387	0	0	0
T24	11061	4	0	0
T25	1673	8	0	0
T26	671	0	0	0
T27	2073	13	0	0
T28	1206	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T24
1	1	Covered	T4,T6,T24

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	493199037	4625	0	0
g_div2.Div2Whole_A	493199037	5383	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493199037	4625	0	0
T2	0	27	0	0
T4	13165	7	0	0
T5	4891	0	0	0
T6	2377	8	0	0
T15	0	5	0	0
T16	0	3	0	0
T17	0	4	0	0
T22	1400	0	0	0
T23	2826	0	0	0
T24	20494	4	0	0
T25	3185	7	0	0
T26	1475	0	0	0
T27	3572	12	0	0
T28	2244	4	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493199037	5383	0	0
T4	13165	7	0	0
T5	4891	0	0	0
T6	2377	11	0	0
T15	0	4	0	0
T16	0	3	0	0
T17	0	5	0	0
T18	0	1	0	0
T22	1400	0	0	0
T23	2826	0	0	0
T24	20494	4	0	0
T25	3185	9	0	0
T26	1475	0	0	0
T27	3572	13	0	0
T28	2244	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T24
1	1	Covered	T4,T6,T24

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	245720438	4540	0	0
g_div4.Div4Whole_A	245720438	5112	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245720438	4540	0	0
T2	0	22	0	0
T4	6864	7	0	0
T5	2434	0	0	0
T6	1312	7	0	0
T15	0	5	0	0
T16	0	3	0	0
T17	0	4	0	0
T22	667	0	0	0
T23	1387	0	0	0
T24	11061	4	0	0
T25	1673	7	0	0
T26	671	0	0	0
T27	2073	12	0	0
T28	1206	4	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245720438	5112	0	0
T4	6864	7	0	0
T5	2434	0	0	0
T6	1312	7	0	0
T15	0	4	0	0
T16	0	3	0	0
T17	0	5	0	0
T18	0	1	0	0
T22	667	0	0	0
T23	1387	0	0	0
T24	11061	4	0	0
T25	1673	8	0	0
T26	671	0	0	0
T27	2073	13	0	0
T28	1206	7	0	0