Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	48007	0	0
CgEnOn_A	2147483647	38124	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48007	0	0
T1	967988	31	0	0
T4	23458	3	0	0
T5	13636	9	0	0
T6	6816	3	0	0
T10	1921837	0	0	0
T22	3857	7	0	0
T23	7850	7	0	0
T24	58432	3	0	0
T25	9009	3	0	0
T26	4015	3	0	0
T27	10402	3	0	0
T28	6389	3	0	0
T35	190879	0	0	0
T41	10124	30	0	0
T42	5427	10	0	0
T43	0	25	0	0
T66	0	5	0	0
T90	69412	0	0	0
T129	23872	0	0	0
T138	2852	0	0	0
T155	0	15	0	0
T156	0	20	0	0
T157	0	5	0	0
T158	0	30	0	0
T159	0	15	0	0
T160	0	30	0	0
T162	4130	0	0	0
T163	13413	0	0	0
T164	9810	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38124	0	0
T1	2452606	62	0	0
T2	0	446	0	0
T5	5095	6	0	0
T8	0	99	0	0
T9	0	171	0	0
T10	1921837	0	0	0
T15	7225	0	0	0
T16	12161	0	0	0
T20	0	4	0	0
T22	3857	4	0	0
T23	7850	4	0	0
T24	58432	0	0	0
T25	9009	0	0	0
T26	4015	0	0	0
T27	10402	0	0	0
T28	6389	0	0	0
T35	190879	0	0	0
T41	10124	48	0	0
T42	5427	10	0	0
T43	0	25	0	0
T49	0	41	0	0
T66	0	4	0	0
T90	69412	0	0	0
T103	0	4	0	0
T129	23872	0	0	0
T138	2852	0	0	0
T155	0	15	0	0
T156	0	20	0	0
T157	0	5	0	0
T158	0	30	0	0
T159	0	15	0	0
T160	0	30	0	0
T161	0	4	0	0
T162	4130	0	0	0
T163	13413	0	0	0
T164	9810	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	245720031	168	0	0
CgEnOn_A	245720031	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245720031	168	0	0
T10	711808	0	0	0
T35	30021	0	0	0
T41	2238	6	0	0
T42	1185	2	0	0
T43	0	5	0	0
T66	0	1	0	0
T90	9115	0	0	0
T129	5462	0	0	0
T138	616	0	0	0
T155	0	3	0	0
T156	0	4	0	0
T157	0	1	0	0
T158	0	6	0	0
T159	0	3	0	0
T160	0	6	0	0
T162	894	0	0	0
T163	3179	0	0	0
T164	2159	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245720031	168	0	0
T10	711808	0	0	0
T35	30021	0	0	0
T41	2238	6	0	0
T42	1185	2	0	0
T43	0	5	0	0
T66	0	1	0	0
T90	9115	0	0	0
T129	5462	0	0	0
T138	616	0	0	0
T155	0	3	0	0
T156	0	4	0	0
T157	0	1	0	0
T158	0	6	0	0
T159	0	3	0	0
T160	0	6	0	0
T162	894	0	0	0
T163	3179	0	0	0
T164	2159	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	122859369	168	0	0
CgEnOn_A	122859369	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122859369	168	0	0
T10	355903	0	0	0
T35	15009	0	0	0
T41	1119	6	0	0
T42	593	2	0	0
T43	0	5	0	0
T66	0	1	0	0
T90	4558	0	0	0
T129	2730	0	0	0
T138	308	0	0	0
T155	0	3	0	0
T156	0	4	0	0
T157	0	1	0	0
T158	0	6	0	0
T159	0	3	0	0
T160	0	6	0	0
T162	447	0	0	0
T163	1590	0	0	0
T164	1080	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122859369	168	0	0
T10	355903	0	0	0
T35	15009	0	0	0
T41	1119	6	0	0
T42	593	2	0	0
T43	0	5	0	0
T66	0	1	0	0
T90	4558	0	0	0
T129	2730	0	0	0
T138	308	0	0	0
T155	0	3	0	0
T156	0	4	0	0
T157	0	1	0	0
T158	0	6	0	0
T159	0	3	0	0
T160	0	6	0	0
T162	447	0	0	0
T163	1590	0	0	0
T164	1080	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	493198602	168	0	0
CgEnOn_A	493198602	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493198602	168	0	0
T10	142320	0	0	0
T35	115831	0	0	0
T41	4529	6	0	0
T42	2463	2	0	0
T43	0	5	0	0
T66	0	1	0	0
T90	46623	0	0	0
T129	10220	0	0	0
T138	1312	0	0	0
T155	0	3	0	0
T156	0	4	0	0
T157	0	1	0	0
T158	0	6	0	0
T159	0	3	0	0
T160	0	6	0	0
T162	1895	0	0	0
T163	5464	0	0	0
T164	4411	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493198602	157	0	0
T10	142320	0	0	0
T35	115831	0	0	0
T41	4529	6	0	0
T42	2463	2	0	0
T43	0	5	0	0
T90	46623	0	0	0
T129	10220	0	0	0
T138	1312	0	0	0
T155	0	3	0	0
T156	0	4	0	0
T157	0	1	0	0
T158	0	6	0	0
T159	0	3	0	0
T160	0	6	0	0
T161	0	4	0	0
T162	1895	0	0	0
T163	5464	0	0	0
T164	4411	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	525808928	158	0	0
CgEnOn_A	525808928	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525808928	158	0	0
T10	149579	1	0	0
T35	120660	0	0	0
T41	4910	4	0	0
T42	2541	1	0	0
T43	0	3	0	0
T64	0	1	0	0
T90	48568	0	0	0
T129	10647	0	0	0
T138	1367	0	0	0
T155	0	5	0	0
T156	0	4	0	0
T157	0	2	0	0
T158	0	4	0	0
T162	1974	0	0	0
T163	5692	0	0	0
T164	4595	0	0	0
T165	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525808928	155	0	0
T10	149579	1	0	0
T35	120660	0	0	0
T41	4910	4	0	0
T42	2541	1	0	0
T43	0	3	0	0
T90	48568	0	0	0
T129	10647	0	0	0
T138	1367	0	0	0
T155	0	5	0	0
T156	0	4	0	0
T157	0	2	0	0
T158	0	4	0	0
T159	0	3	0	0
T162	1974	0	0	0
T163	5692	0	0	0
T164	4595	0	0	0
T165	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	122859369	168	0	0
CgEnOn_A	122859369	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122859369	168	0	0
T10	355903	0	0	0
T35	15009	0	0	0
T41	1119	6	0	0
T42	593	2	0	0
T43	0	5	0	0
T66	0	1	0	0
T90	4558	0	0	0
T129	2730	0	0	0
T138	308	0	0	0
T155	0	3	0	0
T156	0	4	0	0
T157	0	1	0	0
T158	0	6	0	0
T159	0	3	0	0
T160	0	6	0	0
T162	447	0	0	0
T163	1590	0	0	0
T164	1080	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122859369	168	0	0
T10	355903	0	0	0
T35	15009	0	0	0
T41	1119	6	0	0
T42	593	2	0	0
T43	0	5	0	0
T66	0	1	0	0
T90	4558	0	0	0
T129	2730	0	0	0
T138	308	0	0	0
T155	0	3	0	0
T156	0	4	0	0
T157	0	1	0	0
T158	0	6	0	0
T159	0	3	0	0
T160	0	6	0	0
T162	447	0	0	0
T163	1590	0	0	0
T164	1080	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	525808928	158	0	0
CgEnOn_A	525808928	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525808928	158	0	0
T10	149579	1	0	0
T35	120660	0	0	0
T41	4910	4	0	0
T42	2541	1	0	0
T43	0	3	0	0
T64	0	1	0	0
T90	48568	0	0	0
T129	10647	0	0	0
T138	1367	0	0	0
T155	0	5	0	0
T156	0	4	0	0
T157	0	2	0	0
T158	0	4	0	0
T162	1974	0	0	0
T163	5692	0	0	0
T164	4595	0	0	0
T165	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525808928	155	0	0
T10	149579	1	0	0
T35	120660	0	0	0
T41	4910	4	0	0
T42	2541	1	0	0
T43	0	3	0	0
T90	48568	0	0	0
T129	10647	0	0	0
T138	1367	0	0	0
T155	0	5	0	0
T156	0	4	0	0
T157	0	2	0	0
T158	0	4	0	0
T159	0	3	0	0
T162	1974	0	0	0
T163	5692	0	0	0
T164	4595	0	0	0
T165	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	122859369	168	0	0
CgEnOn_A	122859369	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122859369	168	0	0
T10	355903	0	0	0
T35	15009	0	0	0
T41	1119	6	0	0
T42	593	2	0	0
T43	0	5	0	0
T66	0	1	0	0
T90	4558	0	0	0
T129	2730	0	0	0
T138	308	0	0	0
T155	0	3	0	0
T156	0	4	0	0
T157	0	1	0	0
T158	0	6	0	0
T159	0	3	0	0
T160	0	6	0	0
T162	447	0	0	0
T163	1590	0	0	0
T164	1080	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122859369	168	0	0
T10	355903	0	0	0
T35	15009	0	0	0
T41	1119	6	0	0
T42	593	2	0	0
T43	0	5	0	0
T66	0	1	0	0
T90	4558	0	0	0
T129	2730	0	0	0
T138	308	0	0	0
T155	0	3	0	0
T156	0	4	0	0
T157	0	1	0	0
T158	0	6	0	0
T159	0	3	0	0
T160	0	6	0	0
T162	447	0	0	0
T163	1590	0	0	0
T164	1080	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	245720031	7707	0	0
CgEnOn_A	245720031	5249	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245720031	7707	0	0
T4	6863	1	0	0
T5	2433	1	0	0
T6	1311	1	0	0
T22	667	2	0	0
T23	1387	2	0	0
T24	11061	1	0	0
T25	1673	1	0	0
T26	670	1	0	0
T27	2073	1	0	0
T28	1205	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245720031	5249	0	0
T1	424010	10	0	0
T2	0	133	0	0
T8	0	32	0	0
T9	0	42	0	0
T15	2176	0	0	0
T16	3556	0	0	0
T20	0	1	0	0
T22	667	1	0	0
T23	1387	1	0	0
T24	11061	0	0	0
T25	1673	0	0	0
T26	670	0	0	0
T27	2073	0	0	0
T28	1205	0	0	0
T41	0	6	0	0
T49	0	13	0	0
T103	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	122859369	7664	0	0
CgEnOn_A	122859369	5206	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122859369	7664	0	0
T4	3431	1	0	0
T5	1217	1	0	0
T6	653	1	0	0
T22	333	2	0	0
T23	693	2	0	0
T24	5529	1	0	0
T25	835	1	0	0
T26	335	1	0	0
T27	1035	1	0	0
T28	602	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122859369	5206	0	0
T1	212004	10	0	0
T2	0	124	0	0
T8	0	30	0	0
T9	0	38	0	0
T15	1088	0	0	0
T16	1778	0	0	0
T20	0	1	0	0
T22	333	1	0	0
T23	693	1	0	0
T24	5529	0	0	0
T25	835	0	0	0
T26	335	0	0	0
T27	1035	0	0	0
T28	602	0	0	0
T41	0	6	0	0
T49	0	14	0	0
T103	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	493198602	7690	0	0
CgEnOn_A	493198602	5221	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493198602	7690	0	0
T4	13164	1	0	0
T5	4891	1	0	0
T6	2377	1	0	0
T22	1399	2	0	0
T23	2826	2	0	0
T24	20494	1	0	0
T25	3184	1	0	0
T26	1474	1	0	0
T27	3572	1	0	0
T28	2244	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493198602	5221	0	0
T1	848604	11	0	0
T2	0	137	0	0
T8	0	29	0	0
T9	0	36	0	0
T15	3961	0	0	0
T16	6827	0	0	0
T20	0	1	0	0
T22	1399	1	0	0
T23	2826	1	0	0
T24	20494	0	0	0
T25	3184	0	0	0
T26	1474	0	0	0
T27	3572	0	0	0
T28	2244	0	0	0
T41	0	6	0	0
T49	0	14	0	0
T103	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	252521490	7638	0	0
CgEnOn_A	252521490	5169	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252521490	7638	0	0
T4	6582	1	0	0
T5	2446	1	0	0
T6	1189	1	0	0
T22	700	2	0	0
T23	1412	2	0	0
T24	10247	1	0	0
T25	1592	1	0	0
T26	737	1	0	0
T27	1786	1	0	0
T28	1122	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252521490	5169	0	0
T1	453121	8	0	0
T2	0	126	0	0
T8	0	33	0	0
T9	0	39	0	0
T15	1980	0	0	0
T16	3413	0	0	0
T20	0	1	0	0
T22	700	1	0	0
T23	1412	1	0	0
T24	10247	0	0	0
T25	1592	0	0	0
T26	737	0	0	0
T27	1786	0	0	0
T28	1122	0	0	0
T41	0	5	0	0
T49	0	16	0	0
T103	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T2
1	0	Covered	T5,T22,T23
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	525808928	4033	0	0
CgEnOn_A	525808928	4030	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525808928	4033	0	0
T1	967988	31	0	0
T2	0	52	0	0
T5	5095	6	0	0
T6	2475	0	0	0
T8	0	8	0	0
T9	0	55	0	0
T20	0	1	0	0
T22	1458	1	0	0
T23	2944	1	0	0
T24	21348	0	0	0
T25	3317	0	0	0
T26	1536	0	0	0
T27	3722	0	0	0
T28	2338	0	0	0
T103	0	1	0	0
T104	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525808928	4030	0	0
T1	967988	31	0	0
T2	0	52	0	0
T5	5095	6	0	0
T6	2475	0	0	0
T8	0	8	0	0
T9	0	55	0	0
T20	0	1	0	0
T22	1458	1	0	0
T23	2944	1	0	0
T24	21348	0	0	0
T25	3317	0	0	0
T26	1536	0	0	0
T27	3722	0	0	0
T28	2338	0	0	0
T103	0	1	0	0
T104	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T2
1	0	Covered	T5,T22,T23
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	525808928	4011	0	0
CgEnOn_A	525808928	4008	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525808928	4011	0	0
T1	967988	29	0	0
T2	0	54	0	0
T5	5095	8	0	0
T6	2475	0	0	0
T8	0	8	0	0
T9	0	50	0	0
T20	0	1	0	0
T22	1458	1	0	0
T23	2944	1	0	0
T24	21348	0	0	0
T25	3317	0	0	0
T26	1536	0	0	0
T27	3722	0	0	0
T28	2338	0	0	0
T103	0	1	0	0
T104	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525808928	4008	0	0
T1	967988	29	0	0
T2	0	54	0	0
T5	5095	8	0	0
T6	2475	0	0	0
T8	0	8	0	0
T9	0	50	0	0
T20	0	1	0	0
T22	1458	1	0	0
T23	2944	1	0	0
T24	21348	0	0	0
T25	3317	0	0	0
T26	1536	0	0	0
T27	3722	0	0	0
T28	2338	0	0	0
T103	0	1	0	0
T104	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T2
1	0	Covered	T5,T22,T23
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	525808928	4065	0	0
CgEnOn_A	525808928	4062	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525808928	4065	0	0
T1	967988	25	0	0
T2	0	38	0	0
T5	5095	6	0	0
T6	2475	0	0	0
T8	0	8	0	0
T9	0	50	0	0
T20	0	1	0	0
T22	1458	1	0	0
T23	2944	1	0	0
T24	21348	0	0	0
T25	3317	0	0	0
T26	1536	0	0	0
T27	3722	0	0	0
T28	2338	0	0	0
T103	0	1	0	0
T104	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525808928	4062	0	0
T1	967988	25	0	0
T2	0	38	0	0
T5	5095	6	0	0
T6	2475	0	0	0
T8	0	8	0	0
T9	0	50	0	0
T20	0	1	0	0
T22	1458	1	0	0
T23	2944	1	0	0
T24	21348	0	0	0
T25	3317	0	0	0
T26	1536	0	0	0
T27	3722	0	0	0
T28	2338	0	0	0
T103	0	1	0	0
T104	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T2
1	0	Covered	T5,T22,T23
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	525808928	4043	0	0
CgEnOn_A	525808928	4040	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525808928	4043	0	0
T1	967988	25	0	0
T2	0	50	0	0
T5	5095	4	0	0
T6	2475	0	0	0
T8	0	6	0	0
T9	0	50	0	0
T20	0	1	0	0
T22	1458	1	0	0
T23	2944	1	0	0
T24	21348	0	0	0
T25	3317	0	0	0
T26	1536	0	0	0
T27	3722	0	0	0
T28	2338	0	0	0
T103	0	1	0	0
T104	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525808928	4040	0	0
T1	967988	25	0	0
T2	0	50	0	0
T5	5095	4	0	0
T6	2475	0	0	0
T8	0	6	0	0
T9	0	50	0	0
T20	0	1	0	0
T22	1458	1	0	0
T23	2944	1	0	0
T24	21348	0	0	0
T25	3317	0	0	0
T26	1536	0	0	0
T27	3722	0	0	0
T28	2338	0	0	0
T103	0	1	0	0
T104	0	9	0	0