Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T1
0	1	Covered	T1,T2,T8
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T1
1	0	Covered	T41,T42,T43
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1114301146	13604	0	0
GateOpen_A	1114301146	13604	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114301146	13604	0	0
T1	1937741	23	0	0
T2	0	364	0	0
T8	0	92	0	0
T9	0	98	0	0
T10	0	59	0	0
T15	9207	0	0	0
T16	15576	0	0	0
T17	2246	0	0	0
T20	0	4	0	0
T22	2767	3	0	0
T23	6320	4	0	0
T24	47332	0	0	0
T25	7286	0	0	0
T26	3220	0	0	0
T27	8468	0	0	0
T28	5175	0	0	0
T41	0	23	0	0
T49	0	30	0	0
T103	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114301146	13604	0	0
T1	1937741	23	0	0
T2	0	364	0	0
T8	0	92	0	0
T9	0	98	0	0
T10	0	59	0	0
T15	9207	0	0	0
T16	15576	0	0	0
T17	2246	0	0	0
T20	0	4	0	0
T22	2767	3	0	0
T23	6320	4	0	0
T24	47332	0	0	0
T25	7286	0	0	0
T26	3220	0	0	0
T27	8468	0	0	0
T28	5175	0	0	0
T41	0	23	0	0
T49	0	30	0	0
T103	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T1
0	1	Covered	T1,T2,T8
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T1
1	0	Covered	T41,T42,T43
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	122859770	3373	0	0
GateOpen_A	122859770	3373	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122859770	3373	0	0
T1	212005	6	0	0
T2	0	90	0	0
T8	0	22	0	0
T9	0	25	0	0
T10	0	59	0	0
T15	1089	0	0	0
T16	1778	0	0	0
T17	2246	0	0	0
T20	0	1	0	0
T23	694	1	0	0
T24	5530	0	0	0
T25	836	0	0	0
T26	336	0	0	0
T27	1036	0	0	0
T28	602	0	0	0
T41	0	6	0	0
T49	0	6	0	0
T103	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122859770	3373	0	0
T1	212005	6	0	0
T2	0	90	0	0
T8	0	22	0	0
T9	0	25	0	0
T10	0	59	0	0
T15	1089	0	0	0
T16	1778	0	0	0
T17	2246	0	0	0
T20	0	1	0	0
T23	694	1	0	0
T24	5530	0	0	0
T25	836	0	0	0
T26	336	0	0	0
T27	1036	0	0	0
T28	602	0	0	0
T41	0	6	0	0
T49	0	6	0	0
T103	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T1
0	1	Covered	T1,T2,T8
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T1
1	0	Covered	T41,T42,T43
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	245720438	3403	0	0
GateOpen_A	245720438	3403	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245720438	3403	0	0
T1	424010	6	0	0
T2	0	91	0	0
T8	0	23	0	0
T9	0	26	0	0
T15	2176	0	0	0
T16	3557	0	0	0
T20	0	1	0	0
T22	667	1	0	0
T23	1387	1	0	0
T24	11061	0	0	0
T25	1673	0	0	0
T26	671	0	0	0
T27	2073	0	0	0
T28	1206	0	0	0
T41	0	6	0	0
T49	0	9	0	0
T103	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245720438	3403	0	0
T1	424010	6	0	0
T2	0	91	0	0
T8	0	23	0	0
T9	0	26	0	0
T15	2176	0	0	0
T16	3557	0	0	0
T20	0	1	0	0
T22	667	1	0	0
T23	1387	1	0	0
T24	11061	0	0	0
T25	1673	0	0	0
T26	671	0	0	0
T27	2073	0	0	0
T28	1206	0	0	0
T41	0	6	0	0
T49	0	9	0	0
T103	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T1
0	1	Covered	T1,T2,T8
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T1
1	0	Covered	T41,T42,T43
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	493199037	3435	0	0
GateOpen_A	493199037	3435	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493199037	3435	0	0
T1	848604	6	0	0
T2	0	96	0	0
T8	0	23	0	0
T9	0	23	0	0
T15	3961	0	0	0
T16	6827	0	0	0
T20	0	1	0	0
T22	1400	1	0	0
T23	2826	1	0	0
T24	20494	0	0	0
T25	3185	0	0	0
T26	1475	0	0	0
T27	3572	0	0	0
T28	2244	0	0	0
T41	0	6	0	0
T49	0	7	0	0
T103	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493199037	3435	0	0
T1	848604	6	0	0
T2	0	96	0	0
T8	0	23	0	0
T9	0	23	0	0
T15	3961	0	0	0
T16	6827	0	0	0
T20	0	1	0	0
T22	1400	1	0	0
T23	2826	1	0	0
T24	20494	0	0	0
T25	3185	0	0	0
T26	1475	0	0	0
T27	3572	0	0	0
T28	2244	0	0	0
T41	0	6	0	0
T49	0	7	0	0
T103	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T1
0	1	Covered	T1,T2,T8
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T1
1	0	Covered	T41,T42,T43
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	252521901	3393	0	0
GateOpen_A	252521901	3393	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252521901	3393	0	0
T1	453122	5	0	0
T2	0	87	0	0
T8	0	24	0	0
T9	0	24	0	0
T15	1981	0	0	0
T16	3414	0	0	0
T20	0	1	0	0
T22	700	1	0	0
T23	1413	1	0	0
T24	10247	0	0	0
T25	1592	0	0	0
T26	738	0	0	0
T27	1787	0	0	0
T28	1123	0	0	0
T41	0	5	0	0
T49	0	8	0	0
T103	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252521901	3393	0	0
T1	453122	5	0	0
T2	0	87	0	0
T8	0	24	0	0
T9	0	24	0	0
T15	1981	0	0	0
T16	3414	0	0	0
T20	0	1	0	0
T22	700	1	0	0
T23	1413	1	0	0
T24	10247	0	0	0
T25	1592	0	0	0
T26	738	0	0	0
T27	1787	0	0	0
T28	1123	0	0	0
T41	0	5	0	0
T49	0	8	0	0
T103	0	1	0	0