CSRNG Simulation Results

Friday May 19 2023 07:05:15 UTC

GitHub Revision: `30db5a999`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 2235272161

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	27.971us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	19.328us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	99.417us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	21.000s	339.421us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	4.000s	89.301us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	349.845us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	99.417us	20	20	100.00
		csrng_csr_aliasing	4.000s	89.301us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	6.000s	42.154us	200	200	100.00
V2	alerts	csrng_alert	8.000s	357.545us	500	500	100.00
V2	err	csrng_err	5.000s	20.707us	487	500	97.40
V2	cmds	csrng_cmds	1.467m	7.523ms	50	50	100.00
V2	life cycle	csrng_cmds	1.467m	7.523ms	50	50	100.00
V2	stress_all	csrng_stress_all	1.917m	7.814ms	46	50	92.00
V2	intr_test	csrng_intr_test	4.000s	51.425us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	160.938us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	20.000s	1.756ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	20.000s	1.756ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	19.328us	5	5	100.00
		csrng_csr_rw	4.000s	99.417us	20	20	100.00
		csrng_csr_aliasing	4.000s	89.301us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	88.825us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	19.328us	5	5	100.00
		csrng_csr_rw	4.000s	99.417us	20	20	100.00
		csrng_csr_aliasing	4.000s	89.301us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	88.825us	20	20	100.00
V2		TOTAL			1423	1440	98.82
V2S	tl_intg_err	csrng_sec_cm	7.000s	217.146us	5	5	100.00
		csrng_tl_intg_err	13.000s	444.875us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	144.323us	50	50	100.00
		csrng_csr_rw	4.000s	99.417us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	8.000s	357.545us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	1.917m	7.814ms	46	50	92.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	6.000s	42.154us	200	200	100.00
		csrng_err	5.000s	20.707us	487	500	97.40
		csrng_sec_cm	7.000s	217.146us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	6.000s	42.154us	200	200	100.00
		csrng_err	5.000s	20.707us	487	500	97.40
		csrng_sec_cm	7.000s	217.146us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	6.000s	42.154us	200	200	100.00
		csrng_err	5.000s	20.707us	487	500	97.40
		csrng_sec_cm	7.000s	217.146us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	6.000s	42.154us	200	200	100.00
		csrng_err	5.000s	20.707us	487	500	97.40
		csrng_sec_cm	7.000s	217.146us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	6.000s	42.154us	200	200	100.00
		csrng_err	5.000s	20.707us	487	500	97.40
		csrng_sec_cm	7.000s	217.146us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	6.000s	42.154us	200	200	100.00
		csrng_err	5.000s	20.707us	487	500	97.40
		csrng_sec_cm	7.000s	217.146us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	6.000s	42.154us	200	200	100.00
		csrng_err	5.000s	20.707us	487	500	97.40
		csrng_sec_cm	7.000s	217.146us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	8.000s	357.545us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	6.000s	42.154us	200	200	100.00
		csrng_err	5.000s	20.707us	487	500	97.40
V2S	sec_cm_constants_lc_gated	csrng_stress_all	1.917m	7.814ms	46	50	92.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	8.000s	357.545us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	13.000s	444.875us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	6.000s	42.154us	200	200	100.00
		csrng_err	5.000s	20.707us	487	500	97.40
		csrng_sec_cm	7.000s	217.146us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	6.000s	42.154us	200	200	100.00
		csrng_err	5.000s	20.707us	487	500	97.40
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	6.000s	42.154us	200	200	100.00
		csrng_err	5.000s	20.707us	487	500	97.40
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	6.000s	42.154us	200	200	100.00
		csrng_err	5.000s	20.707us	487	500	97.40
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	6.000s	42.154us	200	200	100.00
		csrng_err	5.000s	20.707us	487	500	97.40
		csrng_sec_cm	7.000s	217.146us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	6.000s	42.154us	200	200	100.00
		csrng_err	5.000s	20.707us	487	500	97.40
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.114h	46.915ms	5	50	10.00
V3		TOTAL			5	50	10.00
		TOTAL			1608	1670	96.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.83	93.35	84.31	95.39	86.47	92.29	98.18	97.50	95.28

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == * has 21 failures:
- Test csrng_stress_all_with_rand_reset has 21 failures.
  - 0.csrng_stress_all_with_rand_reset.465992410
    Line 388, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 19816317293 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x351dcd94) == 0x6
  UVM_INFO @ 19816317293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.csrng_stress_all_with_rand_reset.4057265012
    Line 260, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10001671859 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x4f5b3b94) == 0x6
  UVM_INFO @ 10001671859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == * has 13 failures:
- Test csrng_stress_all_with_rand_reset has 13 failures.
  - 1.csrng_stress_all_with_rand_reset.2413742303
    Line 600, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 26673469570 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x60cec394) == 0x6
  UVM_INFO @ 26673469570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.3645598042
    Line 300, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10001656410 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0xf967c794) == 0x6
  UVM_INFO @ 10001656410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

73.csrng_err.193350688
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/73.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 2892760 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   2892760 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   2892760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

146.csrng_err.554474759
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/146.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 6554393 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   6554393 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   6554393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

101.csrng_err.2537598349
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/101.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 3602080 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 3602080 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 3602080 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   3602080 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   3602080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

149.csrng_err.1528493605
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/149.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 5786149 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 5786149 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 5786149 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   5786149 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   5786149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 4 more failures.

Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:573) scoreboard [scoreboard] Invalid csrng_acmd: * has 5 failures:
- Test csrng_stress_all_with_rand_reset has 5 failures.
  - 18.csrng_stress_all_with_rand_reset.2512593632
    Line 837, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/18.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 46914862764 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 46914862764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.csrng_stress_all_with_rand_reset.2693181729
    Line 448, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/29.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 23299383804 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x0
  UVM_INFO @ 23299383804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_FATAL (csrng_scoreboard.sv:573) scoreboard [scoreboard] Invalid csrng_acmd: * has 3 failures:

Test csrng_stress_all_with_rand_reset has 3 failures.

4.csrng_stress_all_with_rand_reset.3339864366
Line 481, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 30597540967 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 30597540967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.csrng_stress_all_with_rand_reset.3962856126
Line 268, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/13.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 3658340688 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 3658340688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:144) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:

Test csrng_stress_all has 3 failures.

8.csrng_stress_all.2910533530
Line 269, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all/latest/run.log

  UVM_ERROR @ 164541341 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 164541341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.csrng_stress_all.3187769579
Line 257, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/35.csrng_stress_all/latest/run.log

  UVM_ERROR @ 259714147 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 259714147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,TRNULLID: NULL pointer dereference. has 3 failures:

Test csrng_stress_all_with_rand_reset has 3 failures.

33.csrng_stress_all_with_rand_reset.1658598345
Line 234, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/33.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
            Time: 26059435 PS + 12
  Verilog Stack Trace:

35.csrng_stress_all_with_rand_reset.1885994501
Line 237, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/35.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
            Time: 6698714 PS + 13
  Verilog Stack Trace:

... and 1 more failures.

UVM_ERROR (csrng_scoreboard.sv:144) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 12.csrng_stress_all.3604789644
    Line 276, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/12.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 2126034854 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 2126034854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:459) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 174.csrng_err.2603273991
    Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/174.csrng_err/latest/run.log
```
  UVM_ERROR @   6231143 ps: (csr_utils_pkg.sv:459) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   6231143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```