CSRNG Simulation Results

Wednesday September 27 2023 19:02:42 UTC

GitHub Revision: `38769a5e7`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 2962962794

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	8.000s	76.801us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	57.980us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	107.347us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	39.000s	3.669ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	47.999us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	369.241us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	107.347us	20	20	100.00
		csrng_csr_aliasing	5.000s	47.999us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	10.000s	128.152us	200	200	100.00
V2	alerts	csrng_alert	15.000s	94.866us	500	500	100.00
V2	err	csrng_err	13.000s	36.459us	487	500	97.40
V2	cmds	csrng_cmds	7.883m	27.918ms	50	50	100.00
V2	life cycle	csrng_cmds	7.883m	27.918ms	50	50	100.00
V2	stress_all	csrng_stress_all	28.333m	61.400ms	45	50	90.00
V2	intr_test	csrng_intr_test	9.000s	53.797us	50	50	100.00
V2	alert_test	csrng_alert_test	4.000s	35.417us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	12.000s	288.780us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	12.000s	288.780us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	57.980us	5	5	100.00
		csrng_csr_rw	4.000s	107.347us	20	20	100.00
		csrng_csr_aliasing	5.000s	47.999us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	60.943us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	57.980us	5	5	100.00
		csrng_csr_rw	4.000s	107.347us	20	20	100.00
		csrng_csr_aliasing	5.000s	47.999us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	60.943us	20	20	100.00
V2		TOTAL			1422	1440	98.75
V2S	tl_intg_err	csrng_sec_cm	6.000s	279.934us	5	5	100.00
		csrng_tl_intg_err	11.000s	248.563us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	14.389us	50	50	100.00
		csrng_csr_rw	4.000s	107.347us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	15.000s	94.866us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	28.333m	61.400ms	45	50	90.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	10.000s	128.152us	200	200	100.00
		csrng_err	13.000s	36.459us	487	500	97.40
		csrng_sec_cm	6.000s	279.934us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	10.000s	128.152us	200	200	100.00
		csrng_err	13.000s	36.459us	487	500	97.40
		csrng_sec_cm	6.000s	279.934us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	10.000s	128.152us	200	200	100.00
		csrng_err	13.000s	36.459us	487	500	97.40
		csrng_sec_cm	6.000s	279.934us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	10.000s	128.152us	200	200	100.00
		csrng_err	13.000s	36.459us	487	500	97.40
		csrng_sec_cm	6.000s	279.934us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	10.000s	128.152us	200	200	100.00
		csrng_err	13.000s	36.459us	487	500	97.40
		csrng_sec_cm	6.000s	279.934us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	10.000s	128.152us	200	200	100.00
		csrng_err	13.000s	36.459us	487	500	97.40
		csrng_sec_cm	6.000s	279.934us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	10.000s	128.152us	200	200	100.00
		csrng_err	13.000s	36.459us	487	500	97.40
		csrng_sec_cm	6.000s	279.934us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	15.000s	94.866us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	10.000s	128.152us	200	200	100.00
		csrng_err	13.000s	36.459us	487	500	97.40
V2S	sec_cm_constants_lc_gated	csrng_stress_all	28.333m	61.400ms	45	50	90.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	15.000s	94.866us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	11.000s	248.563us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	10.000s	128.152us	200	200	100.00
		csrng_err	13.000s	36.459us	487	500	97.40
		csrng_sec_cm	6.000s	279.934us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	10.000s	128.152us	200	200	100.00
		csrng_err	13.000s	36.459us	487	500	97.40
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	10.000s	128.152us	200	200	100.00
		csrng_err	13.000s	36.459us	487	500	97.40
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	10.000s	128.152us	200	200	100.00
		csrng_err	13.000s	36.459us	487	500	97.40
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	10.000s	128.152us	200	200	100.00
		csrng_err	13.000s	36.459us	487	500	97.40
		csrng_sec_cm	6.000s	279.934us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	10.000s	128.152us	200	200	100.00
		csrng_err	13.000s	36.459us	487	500	97.40
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.988h	953.927ms	36	50	72.00
V3		TOTAL			36	50	72.00
		TOTAL			1638	1670	98.08

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.72	93.22	84.27	95.33	86.47	92.23	100.00	97.33	94.81

Failure Buckets

UVM_FATAL (csrng_scoreboard.sv:584) scoreboard [scoreboard] Invalid csrng_acmd: * has 8 failures:

Test csrng_stress_all_with_rand_reset has 8 failures.

0.csrng_stress_all_with_rand_reset.3244709254
Line 423, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 42979020711 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 42979020711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.csrng_stress_all_with_rand_reset.2703791643
Line 332, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/25.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 38886243196 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 38886243196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 8 failures:

Test csrng_err has 8 failures.

17.csrng_err.2190389659
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/17.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2475796 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2475796 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2475796 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   2475796 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   2475796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

21.csrng_err.2795987390
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/21.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 3470988 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 3470988 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 3470988 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   3470988 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   3470988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 6 more failures.

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:155) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:

Test csrng_stress_all has 3 failures.

11.csrng_stress_all.3195232322
Line 269, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/11.csrng_stress_all/latest/run.log

  UVM_ERROR @ 1548894396 ps: (csrng_scoreboard.sv:155) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1548894396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.csrng_stress_all.2386530896
Line 262, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/25.csrng_stress_all/latest/run.log

  UVM_ERROR @  25482146 ps: (csrng_scoreboard.sv:155) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  25482146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 3 failures:

Test csrng_err has 3 failures.

99.csrng_err.3273907549
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/99.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 5022974 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   5022974 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   5022974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

227.csrng_err.1653379174
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/227.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 12399931 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @  12399931 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  12399931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Job csrng-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test csrng_stress_all_with_rand_reset has 2 failures.
  - 12.csrng_stress_all_with_rand_reset.952096813
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/12.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:5137e2df-eb07-4ab3-bc98-6d5d184a7cb6
```
  - 23.csrng_stress_all_with_rand_reset.2838836516
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/23.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:3f97a03a-7d9c-45f7-ab3c-801d78840965
```

UVM_ERROR (csrng_scoreboard.sv:155) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:

Test csrng_stress_all has 2 failures.

15.csrng_stress_all.1961457089
Line 269, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/15.csrng_stress_all/latest/run.log

  UVM_ERROR @ 20877546623 ps: (csrng_scoreboard.sv:155) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 20877546623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.csrng_stress_all.3585768445
Line 265, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/24.csrng_stress_all/latest/run.log

  UVM_ERROR @ 257513219 ps: (csrng_scoreboard.sv:155) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 257513219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:584) scoreboard [scoreboard] Invalid csrng_acmd: * has 2 failures:
- Test csrng_stress_all_with_rand_reset has 2 failures.
  - 27.csrng_stress_all_with_rand_reset.1073818396
    Line 564, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/27.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 88704812662 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 88704812662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.csrng_stress_all_with_rand_reset.1200640605
    Line 686, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/46.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 36785484134 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 36785484134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,TRNULLID: NULL pointer dereference. has 2 failures:

Test csrng_stress_all_with_rand_reset has 2 failures.

30.csrng_stress_all_with_rand_reset.4066871235
Line 323, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/30.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 294, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4985_4.process_tl_access
            Time: 23928132396 PS + 12
  Verilog Stack Trace:

35.csrng_stress_all_with_rand_reset.3470930901
Line 234, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/35.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 294, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4985_4.process_tl_access
            Time: 35934428 PS + 12
  Verilog Stack Trace:

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test csrng_err has 2 failures.

73.csrng_err.2964455113
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/73.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  73.csrng_err.2964455113
  
  coverage files:
    model(design data) :  /workspace/coverage/default/73.csrng_err.2964455113/icc_238a3628_24e48c5b.ucm
    data               :  /workspace/coverage/default/73.csrng_err.2964455113/icc_238a3628_24e48c5b.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Sep 27, 2023 at 13:42:01 PDT  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:150: simulate] Error 1

277.csrng_err.3183657719
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/277.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  277.csrng_err.3183657719
  
  coverage files:
    model(design data) :  /workspace/coverage/default/277.csrng_err.3183657719/icc_238a3628_24e48c5b.ucm
    data               :  /workspace/coverage/default/277.csrng_err.3183657719/icc_238a3628_24e48c5b.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Sep 27, 2023 at 13:44:39 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:150: simulate] Error 1