CSRNG Simulation Results

Sunday October 15 2023 19:02:25 UTC

GitHub Revision: `b2a255f8a`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 1600673825

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	11.000s	64.095us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	12.000s	25.364us	5	5	100.00
V1	csr_rw	csrng_csr_rw	16.000s	50.272us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	32.000s	2.201ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	39.149us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	12.000s	27.603us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	16.000s	50.272us	20	20	100.00
		csrng_csr_aliasing	7.000s	39.149us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	15.000s	41.540us	200	200	100.00
V2	alerts	csrng_alert	24.000s	126.627us	500	500	100.00
V2	err	csrng_err	22.000s	54.244us	488	500	97.60
V2	cmds	csrng_cmds	9.400m	52.809ms	50	50	100.00
V2	life cycle	csrng_cmds	9.400m	52.809ms	50	50	100.00
V2	stress_all	csrng_stress_all	21.200m	56.428ms	48	50	96.00
V2	intr_test	csrng_intr_test	12.000s	13.533us	50	50	100.00
V2	alert_test	csrng_alert_test	14.000s	19.957us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	16.000s	225.551us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	16.000s	225.551us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	12.000s	25.364us	5	5	100.00
		csrng_csr_rw	16.000s	50.272us	20	20	100.00
		csrng_csr_aliasing	7.000s	39.149us	5	5	100.00
		csrng_same_csr_outstanding	14.000s	18.107us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	12.000s	25.364us	5	5	100.00
		csrng_csr_rw	16.000s	50.272us	20	20	100.00
		csrng_csr_aliasing	7.000s	39.149us	5	5	100.00
		csrng_same_csr_outstanding	14.000s	18.107us	20	20	100.00
V2		TOTAL			1426	1440	99.03
V2S	tl_intg_err	csrng_sec_cm	9.000s	102.304us	5	5	100.00
		csrng_tl_intg_err	25.000s	409.333us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	12.000s	14.053us	50	50	100.00
		csrng_csr_rw	16.000s	50.272us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	24.000s	126.627us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	21.200m	56.428ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	15.000s	41.540us	200	200	100.00
		csrng_err	22.000s	54.244us	488	500	97.60
		csrng_sec_cm	9.000s	102.304us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	15.000s	41.540us	200	200	100.00
		csrng_err	22.000s	54.244us	488	500	97.60
		csrng_sec_cm	9.000s	102.304us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	15.000s	41.540us	200	200	100.00
		csrng_err	22.000s	54.244us	488	500	97.60
		csrng_sec_cm	9.000s	102.304us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	15.000s	41.540us	200	200	100.00
		csrng_err	22.000s	54.244us	488	500	97.60
		csrng_sec_cm	9.000s	102.304us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	15.000s	41.540us	200	200	100.00
		csrng_err	22.000s	54.244us	488	500	97.60
		csrng_sec_cm	9.000s	102.304us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	15.000s	41.540us	200	200	100.00
		csrng_err	22.000s	54.244us	488	500	97.60
		csrng_sec_cm	9.000s	102.304us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	15.000s	41.540us	200	200	100.00
		csrng_err	22.000s	54.244us	488	500	97.60
		csrng_sec_cm	9.000s	102.304us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	24.000s	126.627us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	15.000s	41.540us	200	200	100.00
		csrng_err	22.000s	54.244us	488	500	97.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	21.200m	56.428ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	24.000s	126.627us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	25.000s	409.333us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	15.000s	41.540us	200	200	100.00
		csrng_err	22.000s	54.244us	488	500	97.60
		csrng_sec_cm	9.000s	102.304us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	15.000s	41.540us	200	200	100.00
		csrng_err	22.000s	54.244us	488	500	97.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	15.000s	41.540us	200	200	100.00
		csrng_err	22.000s	54.244us	488	500	97.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	15.000s	41.540us	200	200	100.00
		csrng_err	22.000s	54.244us	488	500	97.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	15.000s	41.540us	200	200	100.00
		csrng_err	22.000s	54.244us	488	500	97.60
		csrng_sec_cm	9.000s	102.304us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	15.000s	41.540us	200	200	100.00
		csrng_err	22.000s	54.244us	488	500	97.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.844h	273.159ms	37	50	74.00
V3		TOTAL			37	50	74.00
		TOTAL			1643	1670	98.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.76	93.24	84.31	95.31	86.47	92.29	100.00	97.50	95.64

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 9 failures:

Test csrng_err has 9 failures.

114.csrng_err.656214822
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/114.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 5426073 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   5426073 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   5426073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

116.csrng_err.2740787085
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/116.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 6268140 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   6268140 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   6268140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (csrng_scoreboard.sv:584) scoreboard [scoreboard] Invalid csrng_acmd: * has 6 failures:

Test csrng_stress_all_with_rand_reset has 6 failures.

7.csrng_stress_all_with_rand_reset.3854136477
Line 336, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 17569466211 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 17569466211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.csrng_stress_all_with_rand_reset.4139739693
Line 583, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/20.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 58651222777 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 58651222777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:584) scoreboard [scoreboard] Invalid csrng_acmd: * has 4 failures:
- Test csrng_stress_all_with_rand_reset has 4 failures.
  - 18.csrng_stress_all_with_rand_reset.4041526595
    Line 761, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/18.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 310347351459 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 310347351459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.csrng_stress_all_with_rand_reset.3650029098
    Line 566, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/32.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 324162308595 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 324162308595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,TRNULLID: NULL pointer dereference. has 2 failures:

Test csrng_stress_all_with_rand_reset has 2 failures.

21.csrng_stress_all_with_rand_reset.3204974206
Line 232, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/21.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 294, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4985_4.process_tl_access
            Time: 5605981 PS + 12
  Verilog Stack Trace:

33.csrng_stress_all_with_rand_reset.2136101789
Line 271, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/33.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 294, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4985_4.process_tl_access
            Time: 3287286531 PS + 11
  Verilog Stack Trace:

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 2 failures:

Test csrng_err has 2 failures.

194.csrng_err.4192298964
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/194.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 3097419 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 3097419 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 3097419 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   3097419 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   3097419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

274.csrng_err.2700361422
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/274.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1936119 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1936119 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1936119 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   1936119 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   1936119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:155) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 0.csrng_stress_all.3726247165
    Line 257, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 4611082828 ps: (csrng_scoreboard.sv:155) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 4611082828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csrng_scoreboard.sv:155) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 20.csrng_stress_all.209884771
    Line 256, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/20.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  41762487 ps: (csrng_scoreboard.sv:155) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  41762487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job csrng-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 27.csrng_stress_all_with_rand_reset.1394396631
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/27.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:38e80a5d-8555-4fd2-b4a1-8da9efc7a141
```
UVM_ERROR (csr_utils_pkg.sv:459) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 141.csrng_err.1495666651
    Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/141.csrng_err/latest/run.log
```
  UVM_ERROR @  30506166 ps: (csr_utils_pkg.sv:459) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  30506166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```