CSRNG Simulation Results

Wednesday October 11 2023 19:03:00 UTC

GitHub Revision: `f600eccc2`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 1737291072

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	12.000s	16.081us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	7.000s	28.252us	5	5	100.00
V1	csr_rw	csrng_csr_rw	11.000s	58.416us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	25.000s	676.798us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	10.000s	489.812us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	15.000s	28.393us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	11.000s	58.416us	20	20	100.00
		csrng_csr_aliasing	10.000s	489.812us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	29.000s	43.619us	200	200	100.00
V2	alerts	csrng_alert	22.000s	91.839us	500	500	100.00
V2	err	csrng_err	24.000s	20.418us	485	500	97.00
V2	cmds	csrng_cmds	7.550m	18.896ms	50	50	100.00
V2	life cycle	csrng_cmds	7.550m	18.896ms	50	50	100.00
V2	stress_all	csrng_stress_all	22.350m	114.049ms	50	50	100.00
V2	intr_test	csrng_intr_test	20.000s	207.099us	50	50	100.00
V2	alert_test	csrng_alert_test	14.000s	72.942us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	20.000s	1.534ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	20.000s	1.534ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	7.000s	28.252us	5	5	100.00
		csrng_csr_rw	11.000s	58.416us	20	20	100.00
		csrng_csr_aliasing	10.000s	489.812us	5	5	100.00
		csrng_same_csr_outstanding	16.000s	61.339us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	7.000s	28.252us	5	5	100.00
		csrng_csr_rw	11.000s	58.416us	20	20	100.00
		csrng_csr_aliasing	10.000s	489.812us	5	5	100.00
		csrng_same_csr_outstanding	16.000s	61.339us	20	20	100.00
V2		TOTAL			1425	1440	98.96
V2S	tl_intg_err	csrng_sec_cm	11.000s	53.963us	5	5	100.00
		csrng_tl_intg_err	19.000s	434.451us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	14.000s	36.996us	50	50	100.00
		csrng_csr_rw	11.000s	58.416us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	22.000s	91.839us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	22.350m	114.049ms	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	29.000s	43.619us	200	200	100.00
		csrng_err	24.000s	20.418us	485	500	97.00
		csrng_sec_cm	11.000s	53.963us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	29.000s	43.619us	200	200	100.00
		csrng_err	24.000s	20.418us	485	500	97.00
		csrng_sec_cm	11.000s	53.963us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	29.000s	43.619us	200	200	100.00
		csrng_err	24.000s	20.418us	485	500	97.00
		csrng_sec_cm	11.000s	53.963us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	29.000s	43.619us	200	200	100.00
		csrng_err	24.000s	20.418us	485	500	97.00
		csrng_sec_cm	11.000s	53.963us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	29.000s	43.619us	200	200	100.00
		csrng_err	24.000s	20.418us	485	500	97.00
		csrng_sec_cm	11.000s	53.963us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	29.000s	43.619us	200	200	100.00
		csrng_err	24.000s	20.418us	485	500	97.00
		csrng_sec_cm	11.000s	53.963us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	29.000s	43.619us	200	200	100.00
		csrng_err	24.000s	20.418us	485	500	97.00
		csrng_sec_cm	11.000s	53.963us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	22.000s	91.839us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	29.000s	43.619us	200	200	100.00
		csrng_err	24.000s	20.418us	485	500	97.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	22.350m	114.049ms	50	50	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	22.000s	91.839us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	19.000s	434.451us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	29.000s	43.619us	200	200	100.00
		csrng_err	24.000s	20.418us	485	500	97.00
		csrng_sec_cm	11.000s	53.963us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	29.000s	43.619us	200	200	100.00
		csrng_err	24.000s	20.418us	485	500	97.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	29.000s	43.619us	200	200	100.00
		csrng_err	24.000s	20.418us	485	500	97.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	29.000s	43.619us	200	200	100.00
		csrng_err	24.000s	20.418us	485	500	97.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	29.000s	43.619us	200	200	100.00
		csrng_err	24.000s	20.418us	485	500	97.00
		csrng_sec_cm	11.000s	53.963us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	29.000s	43.619us	200	200	100.00
		csrng_err	24.000s	20.418us	485	500	97.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.771h	360.662ms	35	50	70.00
V3		TOTAL			35	50	70.00
		TOTAL			1640	1670	98.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	8	88.89
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.75	93.22	84.27	95.31	86.47	92.29	100.00	97.50	95.64

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 8 failures:

Test csrng_err has 8 failures.

41.csrng_err.1832700571
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/41.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 7411272 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   7411272 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   7411272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

60.csrng_err.3271088526
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/60.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 17720967 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @  17720967 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  17720967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:584) scoreboard [scoreboard] Invalid csrng_acmd: * has 7 failures:
- Test csrng_stress_all_with_rand_reset has 7 failures.
  - 4.csrng_stress_all_with_rand_reset.3307170912
    Line 925, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 325860534454 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 325860534454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.csrng_stress_all_with_rand_reset.2993709412
    Line 367, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/9.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 8450102736 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 8450102736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

72.csrng_err.1865778553
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/72.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 18949588 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 18949588 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 18949588 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @  18949588 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @  18949588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

85.csrng_err.1406304208
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/85.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 4005348 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 4005348 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 4005348 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   4005348 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   4005348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 4 more failures.

UVM_FATAL (csrng_scoreboard.sv:584) scoreboard [scoreboard] Invalid csrng_acmd: * has 4 failures:

Test csrng_stress_all_with_rand_reset has 4 failures.

1.csrng_stress_all_with_rand_reset.3549945102
Line 671, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 62164716093 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 62164716093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.csrng_stress_all_with_rand_reset.1148307476
Line 912, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/27.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 101761429941 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 101761429941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,TRNULLID: NULL pointer dereference. has 2 failures:

Test csrng_stress_all_with_rand_reset has 2 failures.

8.csrng_stress_all_with_rand_reset.1631335382
Line 234, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 294, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4985_4.process_tl_access
            Time: 48250781 PS + 12
  Verilog Stack Trace:

29.csrng_stress_all_with_rand_reset.1144951815
Line 266, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/29.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 294, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4985_4.process_tl_access
            Time: 2324519444 PS + 12
  Verilog Stack Trace:

Job csrng-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test csrng_stress_all_with_rand_reset has 2 failures.
  - 13.csrng_stress_all_with_rand_reset.1656561771
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/13.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:f4de63f5-c342-4870-9853-f90f1d56735a
```
  - 43.csrng_stress_all_with_rand_reset.1299455964
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/43.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:e581a91f-7b23-4ff8-87cb-9e7aec7af515
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test csrng_err has 1 failures.

68.csrng_err.4232714190
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/68.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  68.csrng_err.4232714190
  
  coverage files:
    model(design data) :  /workspace/coverage/default/68.csrng_err.4232714190/icc_238a3628_24e48c5b.ucm
    data               :  /workspace/coverage/default/68.csrng_err.4232714190/icc_238a3628_24e48c5b.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Oct 11, 2023 at 12:29:40 PDT  (total: 00:00:08)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:173: simulate] Error 1