CSRNG Simulation Results

Wednesday December 27 2023 20:02:24 UTC

GitHub Revision: `0c759b93ab`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 85416116840666724748485424200434981761468351851988553961117902923833034512693

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	12.000s	22.126us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	9.000s	13.187us	5	5	100.00
V1	csr_rw	csrng_csr_rw	15.000s	213.466us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	24.000s	344.855us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	33.230us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	13.000s	20.465us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	15.000s	213.466us	20	20	100.00
		csrng_csr_aliasing	5.000s	33.230us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	22.000s	61.311us	200	200	100.00
V2	alerts	csrng_alert	17.000s	28.162us	500	500	100.00
V2	err	csrng_err	20.000s	24.211us	487	500	97.40
V2	cmds	csrng_cmds	10.583m	62.073ms	50	50	100.00
V2	life cycle	csrng_cmds	10.583m	62.073ms	50	50	100.00
V2	stress_all	csrng_stress_all	27.483m	134.727ms	47	50	94.00
V2	intr_test	csrng_intr_test	13.000s	12.890us	50	50	100.00
V2	alert_test	csrng_alert_test	14.000s	56.458us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	19.000s	615.478us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	19.000s	615.478us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	9.000s	13.187us	5	5	100.00
		csrng_csr_rw	15.000s	213.466us	20	20	100.00
		csrng_csr_aliasing	5.000s	33.230us	5	5	100.00
		csrng_same_csr_outstanding	15.000s	67.340us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	9.000s	13.187us	5	5	100.00
		csrng_csr_rw	15.000s	213.466us	20	20	100.00
		csrng_csr_aliasing	5.000s	33.230us	5	5	100.00
		csrng_same_csr_outstanding	15.000s	67.340us	20	20	100.00
V2		TOTAL			1424	1440	98.89
V2S	tl_intg_err	csrng_sec_cm	9.000s	129.909us	5	5	100.00
		csrng_tl_intg_err	24.000s	1.351ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	11.000s	20.641us	50	50	100.00
		csrng_csr_rw	15.000s	213.466us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	17.000s	28.162us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	27.483m	134.727ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	22.000s	61.311us	200	200	100.00
		csrng_err	20.000s	24.211us	487	500	97.40
		csrng_sec_cm	9.000s	129.909us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	22.000s	61.311us	200	200	100.00
		csrng_err	20.000s	24.211us	487	500	97.40
		csrng_sec_cm	9.000s	129.909us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	22.000s	61.311us	200	200	100.00
		csrng_err	20.000s	24.211us	487	500	97.40
		csrng_sec_cm	9.000s	129.909us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	22.000s	61.311us	200	200	100.00
		csrng_err	20.000s	24.211us	487	500	97.40
		csrng_sec_cm	9.000s	129.909us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	22.000s	61.311us	200	200	100.00
		csrng_err	20.000s	24.211us	487	500	97.40
		csrng_sec_cm	9.000s	129.909us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	22.000s	61.311us	200	200	100.00
		csrng_err	20.000s	24.211us	487	500	97.40
		csrng_sec_cm	9.000s	129.909us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	22.000s	61.311us	200	200	100.00
		csrng_err	20.000s	24.211us	487	500	97.40
		csrng_sec_cm	9.000s	129.909us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	17.000s	28.162us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	22.000s	61.311us	200	200	100.00
		csrng_err	20.000s	24.211us	487	500	97.40
V2S	sec_cm_constants_lc_gated	csrng_stress_all	27.483m	134.727ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	17.000s	28.162us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	24.000s	1.351ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	22.000s	61.311us	200	200	100.00
		csrng_err	20.000s	24.211us	487	500	97.40
		csrng_sec_cm	9.000s	129.909us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	22.000s	61.311us	200	200	100.00
		csrng_err	20.000s	24.211us	487	500	97.40
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	22.000s	61.311us	200	200	100.00
		csrng_err	20.000s	24.211us	487	500	97.40
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	22.000s	61.311us	200	200	100.00
		csrng_err	20.000s	24.211us	487	500	97.40
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	22.000s	61.311us	200	200	100.00
		csrng_err	20.000s	24.211us	487	500	97.40
		csrng_sec_cm	9.000s	129.909us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	22.000s	61.311us	200	200	100.00
		csrng_err	20.000s	24.211us	487	500	97.40
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.699h	354.239ms	38	50	76.00
V3		TOTAL			38	50	76.00
		TOTAL			1642	1670	98.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.77	93.24	84.31	95.35	86.47	92.29	100.00	97.50	95.40

Failure Buckets

UVM_FATAL (csrng_scoreboard.sv:592) scoreboard [scoreboard] Invalid csrng_acmd: * has 9 failures:
- Test csrng_stress_all_with_rand_reset has 9 failures.
  - 3.csrng_stress_all_with_rand_reset.90098574118219893510007322294986094585881892072516330666314206080470253880499
    Line 586, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 69806039771 ps: (csrng_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 69806039771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.csrng_stress_all_with_rand_reset.110810113709739006776457113856000626123634911472156165491091249816344431648859
    Line 708, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/10.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 31030031318 ps: (csrng_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 31030031318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

70.csrng_err.3714970061153103457386194463456368598956454013815152428556554922492471566266
Line 300, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/70.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 1630334 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   1630334 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1630334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

87.csrng_err.50532742214388489135893626280527420050702851878233791227477543470420415651692
Line 300, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/87.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 21730452 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @  21730452 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  21730452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

99.csrng_err.84138328480594451869685139825682264540131326260607425264993272456960989340961
Line 300, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/99.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2542368 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2542368 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2542368 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   2542368 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   2542368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

246.csrng_err.104327501294647341230992900489240912765316394453612571333861480655023349859775
Line 300, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/246.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 3007508 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 3007508 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 3007508 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   3007508 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   3007508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 4 more failures.

Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:592) scoreboard [scoreboard] Invalid csrng_acmd: * has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 9.csrng_stress_all_with_rand_reset.35203903383961476956354018314668493394811782679857595176711959953336441710999
    Line 883, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/9.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 48404715795 ps: (csrng_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 48404715795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.csrng_stress_all_with_rand_reset.93382214178437406289943800280885020352621317547562140254011522099304541817307
    Line 933, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/28.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 64757205805 ps: (csrng_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 64757205805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:158) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 9.csrng_stress_all.26651331308681568800661199338424848545456109781784241369152021043018106037024
    Line 298, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/9.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  31202704 ps: (csrng_scoreboard.sv:158) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  31202704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.csrng_stress_all.43087182052106494594383870257363420435231016575555516273318169223611048290779
    Line 323, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/32.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 2104327005 ps: (csrng_scoreboard.sv:158) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 2104327005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csrng_scoreboard.sv:158) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 0.csrng_stress_all.62698481584772161618388594877503903505811792712182881717907896319960240356547
    Line 309, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 14983896196 ps: (csrng_scoreboard.sv:158) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 14983896196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:459) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 229.csrng_err.90719541223354878934509662457051318610267115747593294842586611325387325164309
    Line 300, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/229.csrng_err/latest/run.log
```
  UVM_ERROR @   8762150 ps: (csr_utils_pkg.sv:459) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   8762150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```