EDN Simulation Results

Friday May 19 2023 07:05:15 UTC

GitHub Revision: 30db5a999

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2235272161

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.960s 51.355us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.910s 16.578us 5 5 100.00
V1 csr_rw edn_csr_rw 0.940s 75.299us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.250s 263.752us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.390s 118.438us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.740s 24.351us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.940s 75.299us 20 20 100.00
edn_csr_aliasing 1.390s 118.438us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.500s 167.802us 50 50 100.00
V2 csrng_commands edn_genbits 1.500s 167.802us 50 50 100.00
V2 genbits edn_genbits 1.500s 167.802us 50 50 100.00
V2 interrupts edn_intr 1.180s 21.247us 50 50 100.00
V2 alerts edn_alert 1.140s 19.312us 50 50 100.00
V2 errs edn_err 1.140s 18.348us 50 50 100.00
V2 disable edn_disable 2.050s 100.000us 49 50 98.00
edn_disable_auto_req_mode 1.170s 317.598us 50 50 100.00
V2 stress_all edn_stress_all 3.920s 173.745us 50 50 100.00
V2 intr_test edn_intr_test 0.900s 17.484us 50 50 100.00
V2 alert_test edn_alert_test 1.790s 82.752us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.930s 2.014ms 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.930s 2.014ms 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.910s 16.578us 5 5 100.00
edn_csr_rw 0.940s 75.299us 20 20 100.00
edn_csr_aliasing 1.390s 118.438us 5 5 100.00
edn_same_csr_outstanding 1.290s 132.757us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.910s 16.578us 5 5 100.00
edn_csr_rw 0.940s 75.299us 20 20 100.00
edn_csr_aliasing 1.390s 118.438us 5 5 100.00
edn_same_csr_outstanding 1.290s 132.757us 20 20 100.00
V2 TOTAL 489 490 99.80
V2S tl_intg_err edn_sec_cm 6.320s 451.077us 5 5 100.00
edn_tl_intg_err 2.660s 219.800us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 0.990s 13.963us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.140s 19.312us 50 50 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.320s 451.077us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.320s 451.077us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.320s 451.077us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.140s 19.312us 50 50 100.00
edn_sec_cm 6.320s 451.077us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.140s 19.312us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.660s 219.800us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.107h 167.733ms 47 50 94.00
V3 TOTAL 47 50 94.00
TOTAL 676 680 99.41

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 10 90.91
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.99 99.03 93.89 96.74 71.71 98.62 99.77 98.14

Failure Buckets

Past Results