V1 |
smoke |
edn_smoke |
0.950s |
48.547us |
50 |
50 |
100.00 |
V1 |
csr_hw_reset |
edn_csr_hw_reset |
0.980s |
20.061us |
5 |
5 |
100.00 |
V1 |
csr_rw |
edn_csr_rw |
0.950s |
14.900us |
20 |
20 |
100.00 |
V1 |
csr_bit_bash |
edn_csr_bit_bash |
5.870s |
268.292us |
5 |
5 |
100.00 |
V1 |
csr_aliasing |
edn_csr_aliasing |
1.510s |
37.653us |
5 |
5 |
100.00 |
V1 |
csr_mem_rw_with_rand_reset |
edn_csr_mem_rw_with_rand_reset |
2.010s |
80.398us |
20 |
20 |
100.00 |
V1 |
regwen_csr_and_corresponding_lockable_csr |
edn_csr_rw |
0.950s |
14.900us |
20 |
20 |
100.00 |
|
|
edn_csr_aliasing |
1.510s |
37.653us |
5 |
5 |
100.00 |
V1 |
|
TOTAL |
|
|
105 |
105 |
100.00 |
V2 |
firmware |
edn_genbits |
1.660s |
179.559us |
50 |
50 |
100.00 |
V2 |
csrng_commands |
edn_genbits |
1.660s |
179.559us |
50 |
50 |
100.00 |
V2 |
genbits |
edn_genbits |
1.660s |
179.559us |
50 |
50 |
100.00 |
V2 |
interrupts |
edn_intr |
1.150s |
19.373us |
50 |
50 |
100.00 |
V2 |
alerts |
edn_alert |
1.100s |
20.004us |
50 |
50 |
100.00 |
V2 |
errs |
edn_err |
1.410s |
20.030us |
100 |
100 |
100.00 |
V2 |
disable |
edn_disable |
0.930s |
16.622us |
49 |
50 |
98.00 |
|
|
edn_disable_auto_req_mode |
1.130s |
131.816us |
50 |
50 |
100.00 |
V2 |
stress_all |
edn_stress_all |
4.870s |
1.535ms |
50 |
50 |
100.00 |
V2 |
intr_test |
edn_intr_test |
0.930s |
18.035us |
50 |
50 |
100.00 |
V2 |
alert_test |
edn_alert_test |
1.190s |
33.553us |
50 |
50 |
100.00 |
V2 |
tl_d_oob_addr_access |
edn_tl_errors |
4.250s |
1.222ms |
20 |
20 |
100.00 |
V2 |
tl_d_illegal_access |
edn_tl_errors |
4.250s |
1.222ms |
20 |
20 |
100.00 |
V2 |
tl_d_outstanding_access |
edn_csr_hw_reset |
0.980s |
20.061us |
5 |
5 |
100.00 |
|
|
edn_csr_rw |
0.950s |
14.900us |
20 |
20 |
100.00 |
|
|
edn_csr_aliasing |
1.510s |
37.653us |
5 |
5 |
100.00 |
|
|
edn_same_csr_outstanding |
1.430s |
31.416us |
20 |
20 |
100.00 |
V2 |
tl_d_partial_access |
edn_csr_hw_reset |
0.980s |
20.061us |
5 |
5 |
100.00 |
|
|
edn_csr_rw |
0.950s |
14.900us |
20 |
20 |
100.00 |
|
|
edn_csr_aliasing |
1.510s |
37.653us |
5 |
5 |
100.00 |
|
|
edn_same_csr_outstanding |
1.430s |
31.416us |
20 |
20 |
100.00 |
V2 |
|
TOTAL |
|
|
539 |
540 |
99.81 |
V2S |
tl_intg_err |
edn_sec_cm |
6.780s |
2.363ms |
5 |
5 |
100.00 |
|
|
edn_tl_intg_err |
2.950s |
130.157us |
20 |
20 |
100.00 |
V2S |
sec_cm_config_regwen |
edn_regwen |
0.920s |
12.593us |
10 |
10 |
100.00 |
V2S |
sec_cm_config_mubi |
edn_alert |
1.100s |
20.004us |
50 |
50 |
100.00 |
V2S |
sec_cm_main_sm_fsm_sparse |
edn_sec_cm |
6.780s |
2.363ms |
5 |
5 |
100.00 |
V2S |
sec_cm_ack_sm_fsm_sparse |
edn_sec_cm |
6.780s |
2.363ms |
5 |
5 |
100.00 |
V2S |
sec_cm_ctr_redun |
edn_sec_cm |
6.780s |
2.363ms |
5 |
5 |
100.00 |
V2S |
sec_cm_main_sm_ctr_local_esc |
edn_alert |
1.100s |
20.004us |
50 |
50 |
100.00 |
|
|
edn_sec_cm |
6.780s |
2.363ms |
5 |
5 |
100.00 |
V2S |
sec_cm_cs_rdata_bus_consistency |
edn_alert |
1.100s |
20.004us |
50 |
50 |
100.00 |
V2S |
sec_cm_tile_link_bus_integrity |
edn_tl_intg_err |
2.950s |
130.157us |
20 |
20 |
100.00 |
V2S |
|
TOTAL |
|
|
35 |
35 |
100.00 |
V3 |
stress_all_with_rand_reset |
edn_stress_all_with_rand_reset |
50.795m |
522.592ms |
50 |
50 |
100.00 |
V3 |
|
TOTAL |
|
|
50 |
50 |
100.00 |
|
|
TOTAL |
|
|
729 |
730 |
99.86 |