Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
12.50						12.50

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	12.50						12.50

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
12.50						12.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
12.50						12.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
82.98		83.33	74.91			90.70	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	1	12.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	1	12.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	210663577	11959030	0	0
boot_gen_cmd_rd_A	210663577	0	0	0
boot_ins_cmd_rd_A	210663577	0	0	0
ctrl_rd_A	210663577	0	0	0
err_code_test_rd_A	210663577	0	0	0
intr_enable_rd_A	210663577	0	0	0
max_num_reqs_between_reseeds_rd_A	210663577	0	0	0
regwen_rd_A	210663577	0	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210663577	11959030	0	0
T1	417033	238821	0	0
T2	417033	238821	0	0
T3	0	238821	0	0
T4	0	238821	0	0
T5	0	238821	0	0
T6	0	238821	0	0
T7	0	238821	0	0
T8	0	238821	0	0
T9	0	238821	0	0
T10	0	238821	0	0
T11	1073	0	0	0
T12	958	0	0	0
T13	985	0	0	0
T14	985	0	0	0
T15	1073	0	0	0
T16	1073	0	0	0
T17	1593	0	0	0
T18	1593	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210663577	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210663577	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210663577	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210663577	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210663577	0	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210663577	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210663577	0	0	0