Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.98		83.33	74.91			90.70

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	82.98		83.33	74.91			90.70

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.98		83.33	74.91			90.70

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.87	97.11	83.08	80.69	50.66	90.48	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	12.50						12.50
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	95.12	100.00				85.71	99.65
u_edn_core	79.14	97.59	77.66	69.31	50.66	89.41	90.22
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.80	96.04	95.27	100.00		92.69	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       99
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T21
0	1	Not Covered
1	0	Covered	T22,T23,T24

 LINE       99
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T21
0	1	Covered	T25,T26,T27
1	0	Covered	T19,T21,T11

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	50	72.46
Total Bits	1168	875	74.91
Total Bits 0->1	584	440	75.34
Total Bits 1->0	584	435	74.49

Ports	69	50	72.46
Port Bits	1168	875	74.91
Port Bits 0->1	584	440	75.34
Port Bits 1->0	584	435	74.49

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
rst_ni	Yes	Yes	T19,T21,T1	Yes	T19,T20,T21	INPUT
tl_i.d_ready	Yes	Yes	T19,T21,T28	Yes	T19,T20,T21	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T20,T21,T28	Yes	T20,T21,T28	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_i.a_address[31:0]	Yes	Yes	T20,T21,T28	Yes	T20,T21,T28	INPUT
tl_i.a_source[7:0]	Yes	Yes	T20,T21,T28	Yes	T20,T21,T28	INPUT
tl_i.a_size[1:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_i.a_valid	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_o.a_ready	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T19,*T20,*T21	Yes	T19,T20,T21	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T20,T28,T1	Yes	T20,T28,T1	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T19,*T20,*T21	Yes	T19,T20,T21	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
edn_i[0].edn_req	Yes	Yes	T20,T21,T1	Yes	T20,T21,T1	INPUT
edn_i[1].edn_req	No	No		No		INPUT
edn_i[2].edn_req	No	No		No		INPUT
edn_i[3].edn_req	No	No		No		INPUT
edn_i[4].edn_req	No	No		No		INPUT
edn_i[5].edn_req	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
edn_i[6].edn_req	Yes	Yes	T19,T12,T13	Yes	T19,T12,T13	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T20,T1,T2	Yes	T20,T1,T2	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T20,T21,T1	Yes	T20,T21,T1	OUTPUT
edn_o[1].edn_bus[31:0]	No	No		No		OUTPUT
edn_o[1].edn_fips	No	No		No		OUTPUT
edn_o[1].edn_ack	No	No		No		OUTPUT
edn_o[2].edn_bus[31:0]	No	No		No		OUTPUT
edn_o[2].edn_fips	No	No		No		OUTPUT
edn_o[2].edn_ack	No	No		No		OUTPUT
edn_o[3].edn_bus[31:0]	No	No		No		OUTPUT
edn_o[3].edn_fips	No	No		No		OUTPUT
edn_o[3].edn_ack	No	No		No		OUTPUT
edn_o[4].edn_bus[31:0]	No	No		No		OUTPUT
edn_o[4].edn_fips	No	No		No		OUTPUT
edn_o[4].edn_ack	No	No		No		OUTPUT
edn_o[5].edn_bus[0]	Yes	Yes	*T29,*T30,*T31	Yes	T29,T30,T31	OUTPUT
edn_o[5].edn_bus[1]	No	No		Yes	T29,T30,T31	OUTPUT
edn_o[5].edn_bus[4:2]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
edn_o[5].edn_bus[5]	No	No		Yes	T29,T30,T31	OUTPUT
edn_o[5].edn_bus[6]	Yes	Yes	*T29,*T30,*T31	Yes	T29,T30,T31	OUTPUT
edn_o[5].edn_bus[7]	No	No		Yes	T29,T30,T31	OUTPUT
edn_o[5].edn_bus[17:8]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
edn_o[5].edn_bus[18]	No	No		Yes	T29,T30,T31	OUTPUT
edn_o[5].edn_bus[21:19]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
edn_o[5].edn_bus[22]	No	No		Yes	T29,T30,T31	OUTPUT
edn_o[5].edn_bus[23]	Yes	Yes	*T29,*T30,*T31	Yes	T29,T30,T31	OUTPUT
edn_o[5].edn_bus[24]	No	No		No		OUTPUT
edn_o[5].edn_bus[26:25]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
edn_o[5].edn_bus[27]	No	No		No		OUTPUT
edn_o[5].edn_bus[31:28]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
edn_o[5].edn_fips	No	No		No		OUTPUT
edn_o[5].edn_ack	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T19,T12,T13	Yes	T19,T12,T13	OUTPUT
edn_o[6].edn_fips	No	No		No		OUTPUT
edn_o[6].edn_ack	Yes	Yes	T19,T12,T13	Yes	T19,T12,T13	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T12,T2	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T3	Yes	T1,T12,T2	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
csrng_cmd_i.csrng_rsp_sts	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T28,T17,T18	Yes	T28,T17,T18	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T19,T21,T28	Yes	T19,T21,T28	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T28,T17,T18	Yes	T28,T17,T18	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T19,T21,T28	Yes	T19,T21,T28	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T21,T1,T11	Yes	T21,T1,T11	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	43	43	100.00	39	90.70
Cover properties	0	0		0
Cover sequences	0	0		0
Total	43	43	100.00	39	90.70

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	209958707	209795607	0	0
CsrngAppIfOut_A	209958707	209795607	0	0
FpvSecCmCntAlertCheck_A	209958707	150	0	0
FpvSecCmMainFsmCheck_A	209958707	100	0	0
FpvSecCmRegWeOnehotCheck_A	209958707	100	0	0
IntrEdnCmdReqDoneKnownO_A	209958707	209795607	0	0
TlAReadyKnownO_A	209958707	209795607	0	0
TlDValidKnownO_A	209958707	209795607	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	209958707	100	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	209958707	100	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	209958707	100	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	209958707	100	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	209958707	100	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	209958707	100	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	209958707	100	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	209958707	387764	0	0
gen_edn_if_asserts[0].EdnDataStable_A	209958707	9830	0	160
gen_edn_if_asserts[0].EdnEndPointOut_A	209958707	209795607	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	209958707	138925	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	209958707	387764	0	0
gen_edn_if_asserts[1].EdnDataStable_A	209958707	0	0	0
gen_edn_if_asserts[1].EdnEndPointOut_A	209958707	209795607	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	209958707	138925	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	209958707	387764	0	0
gen_edn_if_asserts[2].EdnDataStable_A	209958707	0	0	0
gen_edn_if_asserts[2].EdnEndPointOut_A	209958707	209795607	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	209958707	138925	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	209958707	387764	0	0
gen_edn_if_asserts[3].EdnDataStable_A	209958707	0	0	0
gen_edn_if_asserts[3].EdnEndPointOut_A	209958707	209795607	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	209958707	138925	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	209958707	387764	0	0
gen_edn_if_asserts[4].EdnDataStable_A	209958707	0	0	0
gen_edn_if_asserts[4].EdnEndPointOut_A	209958707	209795607	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	209958707	138925	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	209958707	387764	0	0
gen_edn_if_asserts[5].EdnDataStable_A	209958707	150	0	0
gen_edn_if_asserts[5].EdnEndPointOut_A	209958707	209795607	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	209958707	138925	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	209958707	387764	0	0
gen_edn_if_asserts[6].EdnDataStable_A	209958707	147	0	0
gen_edn_if_asserts[6].EdnEndPointOut_A	209958707	209795607	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	209958707	138925	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	209795607	0	0
T1	417033	417022	0	0
T2	417033	417022	0	0
T11	1073	930	0	0
T12	958	898	0	0
T13	985	830	0	0
T14	985	830	0	0
T19	985	830	0	0
T20	1044	982	0	0
T21	1073	930	0	0
T28	1593	1531	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	209795607	0	0
T1	417033	417022	0	0
T2	417033	417022	0	0
T11	1073	930	0	0
T12	958	898	0	0
T13	985	830	0	0
T14	985	830	0	0
T19	985	830	0	0
T20	1044	982	0	0
T21	1073	930	0	0
T28	1593	1531	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	150	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	1	0	0
T12	958	0	0	0
T13	985	0	0	0
T14	985	0	0	0
T15	1073	1	0	0
T16	1073	1	0	0
T21	1073	1	0	0
T25	0	20	0	0
T28	1593	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	100	0	0
T7	417033	0	0	0
T8	417033	0	0	0
T25	35619	20	0	0
T26	0	20	0	0
T27	0	20	0	0
T37	0	20	0	0
T38	0	20	0	0
T39	14373	0	0	0
T40	1086	0	0	0
T41	1593	0	0	0
T42	1086	0	0	0
T43	1593	0	0	0
T44	14373	0	0	0
T45	958	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	100	0	0
T7	417033	0	0	0
T8	417033	0	0	0
T25	35619	20	0	0
T26	0	20	0	0
T27	0	20	0	0
T37	0	20	0	0
T38	0	20	0	0
T39	14373	0	0	0
T40	1086	0	0	0
T41	1593	0	0	0
T42	1086	0	0	0
T43	1593	0	0	0
T44	14373	0	0	0
T45	958	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	209795607	0	0
T1	417033	417022	0	0
T2	417033	417022	0	0
T11	1073	930	0	0
T12	958	898	0	0
T13	985	830	0	0
T14	985	830	0	0
T19	985	830	0	0
T20	1044	982	0	0
T21	1073	930	0	0
T28	1593	1531	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	209795607	0	0
T1	417033	417022	0	0
T2	417033	417022	0	0
T11	1073	930	0	0
T12	958	898	0	0
T13	985	830	0	0
T14	985	830	0	0
T19	985	830	0	0
T20	1044	982	0	0
T21	1073	930	0	0
T28	1593	1531	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	209795607	0	0
T1	417033	417022	0	0
T2	417033	417022	0	0
T11	1073	930	0	0
T12	958	898	0	0
T13	985	830	0	0
T14	985	830	0	0
T19	985	830	0	0
T20	1044	982	0	0
T21	1073	930	0	0
T28	1593	1531	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	100	0	0
T7	417033	0	0	0
T8	417033	0	0	0
T25	35619	20	0	0
T26	0	20	0	0
T27	0	20	0	0
T37	0	20	0	0
T38	0	20	0	0
T39	14373	0	0	0
T40	1086	0	0	0
T41	1593	0	0	0
T42	1086	0	0	0
T43	1593	0	0	0
T44	14373	0	0	0
T45	958	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	100	0	0
T7	417033	0	0	0
T8	417033	0	0	0
T25	35619	20	0	0
T26	0	20	0	0
T27	0	20	0	0
T37	0	20	0	0
T38	0	20	0	0
T39	14373	0	0	0
T40	1086	0	0	0
T41	1593	0	0	0
T42	1086	0	0	0
T43	1593	0	0	0
T44	14373	0	0	0
T45	958	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	100	0	0
T7	417033	0	0	0
T8	417033	0	0	0
T25	35619	20	0	0
T26	0	20	0	0
T27	0	20	0	0
T37	0	20	0	0
T38	0	20	0	0
T39	14373	0	0	0
T40	1086	0	0	0
T41	1593	0	0	0
T42	1086	0	0	0
T43	1593	0	0	0
T44	14373	0	0	0
T45	958	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	100	0	0
T7	417033	0	0	0
T8	417033	0	0	0
T25	35619	20	0	0
T26	0	20	0	0
T27	0	20	0	0
T37	0	20	0	0
T38	0	20	0	0
T39	14373	0	0	0
T40	1086	0	0	0
T41	1593	0	0	0
T42	1086	0	0	0
T43	1593	0	0	0
T44	14373	0	0	0
T45	958	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	100	0	0
T7	417033	0	0	0
T8	417033	0	0	0
T25	35619	20	0	0
T26	0	20	0	0
T27	0	20	0	0
T37	0	20	0	0
T38	0	20	0	0
T39	14373	0	0	0
T40	1086	0	0	0
T41	1593	0	0	0
T42	1086	0	0	0
T43	1593	0	0	0
T44	14373	0	0	0
T45	958	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	100	0	0
T7	417033	0	0	0
T8	417033	0	0	0
T25	35619	20	0	0
T26	0	20	0	0
T27	0	20	0	0
T37	0	20	0	0
T38	0	20	0	0
T39	14373	0	0	0
T40	1086	0	0	0
T41	1593	0	0	0
T42	1086	0	0	0
T43	1593	0	0	0
T44	14373	0	0	0
T45	958	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	100	0	0
T7	417033	0	0	0
T8	417033	0	0	0
T25	35619	20	0	0
T26	0	20	0	0
T27	0	20	0	0
T37	0	20	0	0
T38	0	20	0	0
T39	14373	0	0	0
T40	1086	0	0	0
T41	1593	0	0	0
T42	1086	0	0	0
T43	1593	0	0	0
T44	14373	0	0	0
T45	958	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	387764	0	0
T1	417033	1286	0	0
T2	417033	1286	0	0
T11	1073	506	0	0
T12	958	31	0	0
T13	985	482	0	0
T14	985	482	0	0
T19	985	482	0	0
T20	1044	11	0	0
T21	1073	506	0	0
T28	1593	1530	0	0

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	9830	0	160
T1	417033	122	0	0
T2	417033	122	0	0
T3	0	122	0	0
T4	0	122	0	0
T11	1073	0	0	0
T12	958	0	0	0
T13	985	0	0	0
T14	985	0	0	0
T15	1073	0	0	0
T20	1044	3	0	1
T21	1073	0	0	0
T22	0	4	0	1
T23	0	4	0	1
T24	0	0	0	1
T28	1593	0	0	0
T46	0	3	0	1
T47	0	3	0	1
T48	0	3	0	1
T49	0	0	0	1
T50	0	0	0	1
T51	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	209795607	0	0
T1	417033	417022	0	0
T2	417033	417022	0	0
T11	1073	930	0	0
T12	958	898	0	0
T13	985	830	0	0
T14	985	830	0	0
T19	985	830	0	0
T20	1044	982	0	0
T21	1073	930	0	0
T28	1593	1531	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	138925	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	590	0	0
T12	958	0	0	0
T13	985	442	0	0
T14	985	442	0	0
T15	0	590	0	0
T16	0	590	0	0
T19	985	442	0	0
T20	1044	0	0	0
T21	1073	590	0	0
T28	1593	0	0	0
T32	0	590	0	0
T52	0	442	0	0
T53	0	442	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	387764	0	0
T1	417033	1286	0	0
T2	417033	1286	0	0
T11	1073	506	0	0
T12	958	31	0	0
T13	985	482	0	0
T14	985	482	0	0
T19	985	482	0	0
T20	1044	11	0	0
T21	1073	506	0	0
T28	1593	1530	0	0

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	0	0	0

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	209795607	0	0
T1	417033	417022	0	0
T2	417033	417022	0	0
T11	1073	930	0	0
T12	958	898	0	0
T13	985	830	0	0
T14	985	830	0	0
T19	985	830	0	0
T20	1044	982	0	0
T21	1073	930	0	0
T28	1593	1531	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	138925	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	590	0	0
T12	958	0	0	0
T13	985	442	0	0
T14	985	442	0	0
T15	0	590	0	0
T16	0	590	0	0
T19	985	442	0	0
T20	1044	0	0	0
T21	1073	590	0	0
T28	1593	0	0	0
T32	0	590	0	0
T52	0	442	0	0
T53	0	442	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	387764	0	0
T1	417033	1286	0	0
T2	417033	1286	0	0
T11	1073	506	0	0
T12	958	31	0	0
T13	985	482	0	0
T14	985	482	0	0
T19	985	482	0	0
T20	1044	11	0	0
T21	1073	506	0	0
T28	1593	1530	0	0

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	0	0	0

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	209795607	0	0
T1	417033	417022	0	0
T2	417033	417022	0	0
T11	1073	930	0	0
T12	958	898	0	0
T13	985	830	0	0
T14	985	830	0	0
T19	985	830	0	0
T20	1044	982	0	0
T21	1073	930	0	0
T28	1593	1531	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	138925	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	590	0	0
T12	958	0	0	0
T13	985	442	0	0
T14	985	442	0	0
T15	0	590	0	0
T16	0	590	0	0
T19	985	442	0	0
T20	1044	0	0	0
T21	1073	590	0	0
T28	1593	0	0	0
T32	0	590	0	0
T52	0	442	0	0
T53	0	442	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	387764	0	0
T1	417033	1286	0	0
T2	417033	1286	0	0
T11	1073	506	0	0
T12	958	31	0	0
T13	985	482	0	0
T14	985	482	0	0
T19	985	482	0	0
T20	1044	11	0	0
T21	1073	506	0	0
T28	1593	1530	0	0

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	0	0	0

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	209795607	0	0
T1	417033	417022	0	0
T2	417033	417022	0	0
T11	1073	930	0	0
T12	958	898	0	0
T13	985	830	0	0
T14	985	830	0	0
T19	985	830	0	0
T20	1044	982	0	0
T21	1073	930	0	0
T28	1593	1531	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	138925	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	590	0	0
T12	958	0	0	0
T13	985	442	0	0
T14	985	442	0	0
T15	0	590	0	0
T16	0	590	0	0
T19	985	442	0	0
T20	1044	0	0	0
T21	1073	590	0	0
T28	1593	0	0	0
T32	0	590	0	0
T52	0	442	0	0
T53	0	442	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	387764	0	0
T1	417033	1286	0	0
T2	417033	1286	0	0
T11	1073	506	0	0
T12	958	31	0	0
T13	985	482	0	0
T14	985	482	0	0
T19	985	482	0	0
T20	1044	11	0	0
T21	1073	506	0	0
T28	1593	1530	0	0

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	0	0	0

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	209795607	0	0
T1	417033	417022	0	0
T2	417033	417022	0	0
T11	1073	930	0	0
T12	958	898	0	0
T13	985	830	0	0
T14	985	830	0	0
T19	985	830	0	0
T20	1044	982	0	0
T21	1073	930	0	0
T28	1593	1531	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	138925	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	590	0	0
T12	958	0	0	0
T13	985	442	0	0
T14	985	442	0	0
T15	0	590	0	0
T16	0	590	0	0
T19	985	442	0	0
T20	1044	0	0	0
T21	1073	590	0	0
T28	1593	0	0	0
T32	0	590	0	0
T52	0	442	0	0
T53	0	442	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	387764	0	0
T1	417033	1286	0	0
T2	417033	1286	0	0
T11	1073	506	0	0
T12	958	31	0	0
T13	985	482	0	0
T14	985	482	0	0
T19	985	482	0	0
T20	1044	11	0	0
T21	1073	506	0	0
T28	1593	1530	0	0

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	150	0	0
T4	417033	0	0	0
T29	1469	3	0	0
T30	0	3	0	0
T31	0	3	0	0
T32	1073	0	0	0
T33	1073	0	0	0
T47	1044	0	0	0
T48	1044	0	0	0
T54	0	3	0	0
T55	0	3	0	0
T56	0	3	0	0
T57	0	3	0	0
T58	0	3	0	0
T59	0	3	0	0
T60	0	3	0	0
T61	1593	0	0	0
T62	958	0	0	0
T63	958	0	0	0
T64	1593	0	0	0

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	209795607	0	0
T1	417033	417022	0	0
T2	417033	417022	0	0
T11	1073	930	0	0
T12	958	898	0	0
T13	985	830	0	0
T14	985	830	0	0
T19	985	830	0	0
T20	1044	982	0	0
T21	1073	930	0	0
T28	1593	1531	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	138925	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	590	0	0
T12	958	0	0	0
T13	985	442	0	0
T14	985	442	0	0
T15	0	590	0	0
T16	0	590	0	0
T19	985	442	0	0
T20	1044	0	0	0
T21	1073	590	0	0
T28	1593	0	0	0
T32	0	590	0	0
T52	0	442	0	0
T53	0	442	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	387764	0	0
T1	417033	1286	0	0
T2	417033	1286	0	0
T11	1073	506	0	0
T12	958	31	0	0
T13	985	482	0	0
T14	985	482	0	0
T19	985	482	0	0
T20	1044	11	0	0
T21	1073	506	0	0
T28	1593	1530	0	0

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	147	0	0
T2	417033	0	0	0
T12	958	3	0	0
T13	985	0	0	0
T14	985	0	0	0
T15	1073	0	0	0
T16	1073	0	0	0
T17	1593	0	0	0
T18	1593	0	0	0
T45	0	3	0	0
T46	912	0	0	0
T62	0	3	0	0
T63	0	3	0	0
T65	0	3	0	0
T66	0	3	0	0
T67	0	3	0	0
T68	0	3	0	0
T69	0	3	0	0
T70	0	3	0	0
T71	1593	0	0	0

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	209795607	0	0
T1	417033	417022	0	0
T2	417033	417022	0	0
T11	1073	930	0	0
T12	958	898	0	0
T13	985	830	0	0
T14	985	830	0	0
T19	985	830	0	0
T20	1044	982	0	0
T21	1073	930	0	0
T28	1593	1531	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	138925	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	590	0	0
T12	958	0	0	0
T13	985	442	0	0
T14	985	442	0	0
T15	0	590	0	0
T16	0	590	0	0
T19	985	442	0	0
T20	1044	0	0	0
T21	1073	590	0	0
T28	1593	0	0	0
T32	0	590	0	0
T52	0	442	0	0
T53	0	442	0	0