EDN Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.960s 13.059us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.930s 26.727us 5 5 100.00
V1 csr_rw edn_csr_rw 0.930s 23.248us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.330s 351.971us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.380s 59.184us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.340s 51.164us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.930s 23.248us 20 20 100.00
edn_csr_aliasing 1.380s 59.184us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.220s 17.999us 300 300 100.00
V2 csrng_commands edn_genbits 1.220s 17.999us 300 300 100.00
V2 genbits edn_genbits 1.220s 17.999us 300 300 100.00
V2 interrupts edn_intr 1.180s 18.439us 50 50 100.00
V2 alerts edn_alert 1.050s 18.259us 50 50 100.00
V2 errs edn_err 1.250s 24.964us 100 100 100.00
V2 disable edn_disable 0.990s 12.219us 50 50 100.00
edn_disable_auto_req_mode 0.980s 14.969us 50 50 100.00
V2 stress_all edn_stress_all 4.160s 154.489us 50 50 100.00
V2 intr_test edn_intr_test 0.910s 25.518us 50 50 100.00
V2 alert_test edn_alert_test 0.930s 28.185us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.930s 204.078us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 3.930s 204.078us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.930s 26.727us 5 5 100.00
edn_csr_rw 0.930s 23.248us 20 20 100.00
edn_csr_aliasing 1.380s 59.184us 5 5 100.00
edn_same_csr_outstanding 1.370s 61.976us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.930s 26.727us 5 5 100.00
edn_csr_rw 0.930s 23.248us 20 20 100.00
edn_csr_aliasing 1.380s 59.184us 5 5 100.00
edn_same_csr_outstanding 1.370s 61.976us 20 20 100.00
V2 TOTAL 790 790 100.00
V2S tl_intg_err edn_sec_cm 5.900s 717.216us 5 5 100.00
edn_tl_intg_err 2.540s 155.537us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 0.890s 11.759us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.050s 18.259us 50 50 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 5.900s 717.216us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 5.900s 717.216us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 5.900s 717.216us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.050s 18.259us 50 50 100.00
edn_sec_cm 5.900s 717.216us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.050s 18.259us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.540s 155.537us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 18.526m 41.708ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 980 980 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
88.04 98.64 87.64 94.78 59.21 96.47 96.83 82.73

Past Results