EDN Simulation Results

Sunday October 15 2023 19:02:25 UTC

GitHub Revision: `b2a255f8a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1600673825

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.930s	22.226us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.930s	49.813us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.940s	27.886us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.220s	1.309ms	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.360s	372.965us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.870s	27.668us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.940s	27.886us	20	20	100.00
		edn_csr_aliasing	1.360s	372.965us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.430s	31.710us	50	50	100.00
V2	csrng_commands	edn_genbits	1.430s	31.710us	50	50	100.00
V2	genbits	edn_genbits	1.430s	31.710us	50	50	100.00
V2	interrupts	edn_intr	1.130s	26.363us	50	50	100.00
V2	alerts	edn_alert	1.050s	18.010us	50	50	100.00
V2	errs	edn_err	1.400s	18.542us	100	100	100.00
V2	disable	edn_disable	0.910s	14.666us	49	50	98.00
		edn_disable_auto_req_mode	2.520s	500.000us	49	50	98.00
V2	stress_all	edn_stress_all	4.370s	206.302us	50	50	100.00
V2	intr_test	edn_intr_test	0.960s	17.655us	50	50	100.00
V2	alert_test	edn_alert_test	1.010s	19.063us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.270s	135.808us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.270s	135.808us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.930s	49.813us	5	5	100.00
		edn_csr_rw	0.940s	27.886us	20	20	100.00
		edn_csr_aliasing	1.360s	372.965us	5	5	100.00
		edn_same_csr_outstanding	1.450s	77.732us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.930s	49.813us	5	5	100.00
		edn_csr_rw	0.940s	27.886us	20	20	100.00
		edn_csr_aliasing	1.360s	372.965us	5	5	100.00
		edn_same_csr_outstanding	1.450s	77.732us	20	20	100.00
V2		TOTAL			538	540	99.63
V2S	tl_intg_err	edn_sec_cm	6.160s	1.001ms	5	5	100.00
		edn_tl_intg_err	3.700s	192.469us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.900s	14.801us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.050s	18.010us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.160s	1.001ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.160s	1.001ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.160s	1.001ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.050s	18.010us	50	50	100.00
		edn_sec_cm	6.160s	1.001ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.050s	18.010us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.700s	192.469us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	44.384m	112.715ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			728	730	99.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	9	81.82
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.21	99.02	92.39	96.84	93.42	98.62	99.77	93.40

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

Test edn_disable has 1 failures.

29.edn_disable.2366410768
Line 210, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/29.edn_disable/latest/run.log

  UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test edn_disable_auto_req_mode has 1 failures.

46.edn_disable_auto_req_mode.179092145
Line 210, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/46.edn_disable_auto_req_mode/latest/run.log

  UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---