EDN Simulation Results

Wednesday October 18 2023 19:02:45 UTC

GitHub Revision: `7147be371`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 37197468119938503700577416798371665840263604623132840803912470482854908403453

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.000s	21.768us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.970s	15.899us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.060s	14.091us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.180s	175.970us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.420s	31.808us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.390s	27.768us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.060s	14.091us	20	20	100.00
		edn_csr_aliasing	1.420s	31.808us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.020s	22.643us	50	50	100.00
V2	csrng_commands	edn_genbits	1.020s	22.643us	50	50	100.00
V2	genbits	edn_genbits	1.020s	22.643us	50	50	100.00
V2	interrupts	edn_intr	1.150s	22.373us	50	50	100.00
V2	alerts	edn_alert	1.080s	32.331us	50	50	100.00
V2	errs	edn_err	0.980s	29.872us	100	100	100.00
V2	disable	edn_disable	0.890s	19.977us	49	50	98.00
		edn_disable_auto_req_mode	1.050s	30.622us	50	50	100.00
V2	stress_all	edn_stress_all	3.820s	299.451us	50	50	100.00
V2	intr_test	edn_intr_test	1.090s	15.334us	50	50	100.00
V2	alert_test	edn_alert_test	0.980s	16.111us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.780s	100.515us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.780s	100.515us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.970s	15.899us	5	5	100.00
		edn_csr_rw	1.060s	14.091us	20	20	100.00
		edn_csr_aliasing	1.420s	31.808us	5	5	100.00
		edn_same_csr_outstanding	1.400s	32.384us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.970s	15.899us	5	5	100.00
		edn_csr_rw	1.060s	14.091us	20	20	100.00
		edn_csr_aliasing	1.420s	31.808us	5	5	100.00
		edn_same_csr_outstanding	1.400s	32.384us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	edn_sec_cm	6.120s	359.808us	5	5	100.00
		edn_tl_intg_err	2.540s	87.152us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.870s	19.018us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.080s	32.331us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.120s	359.808us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.120s	359.808us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.120s	359.808us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.080s	32.331us	50	50	100.00
		edn_sec_cm	6.120s	359.808us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.080s	32.331us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.540s	87.152us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	19.184m	86.881ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			729	730	99.86

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
81.90	97.11	83.08	80.69	50.66	90.48	95.24	76.08

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test edn_disable has 1 failures.

8.edn_disable.62671696593417265289850607474042525813838723021790869442512346379350677583749
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/8.edn_disable/latest/run.log

  [make]: simulate
  cd /workspace/8.edn_disable/latest && /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62671696593417265289850607474042525813838723021790869442512346379350677583749 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.62671696593417265289850607474042525813838723021790869442512346379350677583749
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct 18 13:29 2023
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 255