EDN Simulation Results

Wednesday December 20 2023 20:02:55 UTC

GitHub Revision: 9601d3bbdd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30104064247514112511662306974640835321092728874679524971043777466318536599043

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.950s	20.039us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.970s	63.521us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.910s	12.888us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.980s	226.332us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.460s	72.623us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.710s	88.146us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.910s	12.888us	20	20	100.00
		edn_csr_aliasing	1.460s	72.623us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	4.160m	10.012ms	299	300	99.67
V2	csrng_commands	edn_genbits	4.160m	10.012ms	299	300	99.67
V2	genbits	edn_genbits	4.160m	10.012ms	299	300	99.67
V2	interrupts	edn_intr	1.180s	20.777us	50	50	100.00
V2	alerts	edn_alert	1.080s	21.342us	50	50	100.00
V2	errs	edn_err	1.420s	19.845us	100	100	100.00
V2	disable	edn_disable	0.920s	13.287us	47	50	94.00
		edn_disable_auto_req_mode	1.200s	335.730us	50	50	100.00
V2	stress_all	edn_stress_all	5.090s	2.433ms	50	50	100.00
V2	intr_test	edn_intr_test	0.950s	18.374us	50	50	100.00
V2	alert_test	edn_alert_test	1.420s	220.190us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	5.220s	948.098us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	5.220s	948.098us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.970s	63.521us	5	5	100.00
		edn_csr_rw	0.910s	12.888us	20	20	100.00
		edn_csr_aliasing	1.460s	72.623us	5	5	100.00
		edn_same_csr_outstanding	1.320s	64.996us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.970s	63.521us	5	5	100.00
		edn_csr_rw	0.910s	12.888us	20	20	100.00
		edn_csr_aliasing	1.460s	72.623us	5	5	100.00
		edn_same_csr_outstanding	1.320s	64.996us	20	20	100.00
V2		TOTAL			786	790	99.49
V2S	tl_intg_err	edn_sec_cm	7.600s	531.446us	5	5	100.00
		edn_tl_intg_err	2.620s	92.751us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.910s	74.121us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.080s	21.342us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.600s	531.446us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.600s	531.446us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.600s	531.446us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.080s	21.342us	50	50	100.00
		edn_sec_cm	7.600s	531.446us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.080s	21.342us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.620s	92.751us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	38.689m	98.618ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			974	980	99.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	9	81.82
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.72	99.02	92.39	96.79	91.45	98.62	99.77	99.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

  • Test edn_disable has 3 failures.

    • 11.edn_disable.9342220374515800898900666553856714697782480239316650633793394627346151610849
      Line 255, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/11.edn_disable/latest/run.log

        UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 37.edn_disable.100061965210611503797572841663698436613541315402307713533009734547808728198189
      Line 255, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/37.edn_disable/latest/run.log

        UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL (edn_scoreboard.sv:381) [scoreboard] Check failed (!instantiated) Instantiate command not allowed for instantiated CSRNG instance. the value from generate fifo *. has 2 failures:

  • Test edn_stress_all_with_rand_reset has 2 failures.

    • 10.edn_stress_all_with_rand_reset.20452233497422960345305452503891237335990847439719719497128279877156593908471
      Line 476, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/10.edn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 48362637326 ps: (edn_scoreboard.sv:381) [uvm_test_top.env.scoreboard] Check failed (!instantiated) Instantiate command not allowed for instantiated CSRNG instance. the value from generate fifo 0x00000901.
        UVM_INFO @ 48362637326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 27.edn_stress_all_with_rand_reset.19625807141315155656911288981160676122938323697005531213595953089226039291072
      Line 331, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/27.edn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 29660137385 ps: (edn_scoreboard.sv:381) [uvm_test_top.env.scoreboard] Check failed (!instantiated) Instantiate command not allowed for instantiated CSRNG instance. the value from generate fifo 0x00000901.
        UVM_INFO @ 29660137385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout edn_reg_block.main_sm_state (addr=*) == * has 1 failures:

  • Test edn_genbits has 1 failures.

    • 290.edn_genbits.106925442075336441190860618985145825005649491076151827312914015460514872848515
      Line 253, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/290.edn_genbits/latest/run.log

        UVM_FATAL @ 10012258478 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout edn_reg_block.main_sm_state (addr=0x12160e40) == 0x185
        UVM_INFO @ 10012258478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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