EDN Simulation Results

Sunday December 24 2023 20:02:26 UTC

GitHub Revision: `671f2b57e2`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96716765175854174075659971574604807242747408006700796360560480210023744343645

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.020s	27.401us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.010s	18.506us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.990s	20.013us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.250s	61.608us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.480s	70.105us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.460s	133.142us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.990s	20.013us	20	20	100.00
		edn_csr_aliasing	1.480s	70.105us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	4.910s	577.078us	300	300	100.00
V2	csrng_commands	edn_genbits	4.910s	577.078us	300	300	100.00
V2	genbits	edn_genbits	4.910s	577.078us	300	300	100.00
V2	interrupts	edn_intr	1.160s	17.711us	50	50	100.00
V2	alerts	edn_alert	1.060s	21.189us	50	50	100.00
V2	errs	edn_err	1.430s	18.206us	100	100	100.00
V2	disable	edn_disable	0.950s	20.908us	48	50	96.00
		edn_disable_auto_req_mode	1.340s	28.614us	50	50	100.00
V2	stress_all	edn_stress_all	4.410s	207.527us	50	50	100.00
V2	intr_test	edn_intr_test	0.930s	16.299us	50	50	100.00
V2	alert_test	edn_alert_test	1.220s	45.572us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.230s	235.667us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.230s	235.667us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.010s	18.506us	5	5	100.00
		edn_csr_rw	0.990s	20.013us	20	20	100.00
		edn_csr_aliasing	1.480s	70.105us	5	5	100.00
		edn_same_csr_outstanding	1.300s	27.284us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.010s	18.506us	5	5	100.00
		edn_csr_rw	0.990s	20.013us	20	20	100.00
		edn_csr_aliasing	1.480s	70.105us	5	5	100.00
		edn_same_csr_outstanding	1.300s	27.284us	20	20	100.00
V2		TOTAL			788	790	99.75
V2S	tl_intg_err	edn_sec_cm	6.660s	1.513ms	5	5	100.00
		edn_tl_intg_err	3.240s	144.954us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.950s	13.568us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.060s	21.189us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.660s	1.513ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.660s	1.513ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.660s	1.513ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.060s	21.189us	50	50	100.00
		edn_sec_cm	6.660s	1.513ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.060s	21.189us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.240s	144.954us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	52.331m	626.651ms	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			975	980	99.49

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.75	99.02	92.39	96.79	91.45	98.62	99.77	99.20

Failure Buckets

Job edn-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test edn_stress_all_with_rand_reset has 2 failures.
  - 14.edn_stress_all_with_rand_reset.73829528896482396452506050367597558770748339404311446549473594320897929085964
    Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/14.edn_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:9dd6af70-c9bd-4523-b49f-6917151a55f7
```
  - 26.edn_stress_all_with_rand_reset.55575984303203767626825036843045300718592163723612503862334227331464887280326
    Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/26.edn_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:7413f911-a070-476a-a8d6-d7904ce6bf68
```
Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
- Test edn_disable has 1 failures.
  - 7.edn_disable.1565958961590481076390660145299898034505401297712900562701266496909353959025
    Line 256, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/7.edn_disable/latest/run.log
```
      Offending '(d2h.d_error || ((d2h.d_data & 'h0000ffff) == (exp_vals[4] & 'h0000ffff)))'
  UVM_ERROR @  21488049 ps: (edn_csr_assert_fpv.sv:188) [ASSERT FAILED] ctrl_rd_A
  UVM_INFO @  21488049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test edn_disable has 1 failures.
  - 37.edn_disable.109593280153211302666580296194577144425079863582247101336399135406922105372284
    Line 255, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/37.edn_disable/latest/run.log
```
  UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (edn_scoreboard.sv:381) [scoreboard] Check failed (!instantiated) Instantiate command not allowed for instantiated CSRNG instance. the value from generate fifo *. has 1 failures:
- Test edn_stress_all_with_rand_reset has 1 failures.
  - 38.edn_stress_all_with_rand_reset.1127660000708720929806688738897515113475901355393325931412508413882921022910
    Line 601, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/38.edn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 448637983386 ps: (edn_scoreboard.sv:381) [uvm_test_top.env.scoreboard] Check failed (!instantiated) Instantiate command not allowed for instantiated CSRNG instance. the value from generate fifo 0x00000901.
  UVM_INFO @ 448637983386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

EDN Simulation Results

Sunday December 24 2023 20:02:26 UTC

GitHub Revision: 671f2b57e2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96716765175854174075659971574604807242747408006700796360560480210023744343645

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `671f2b57e2`