Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.15	100.00	100.00		90.74	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	98.15	100.00	100.00		90.74	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.15	100.00	100.00		90.74	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.15	100.00	100.00		90.74	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.57	100.00	89.71			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		103	103	100.00
ALWAYS	40	3	3	100.00
CONT_ASSIGN	42	1	1	100.00
ALWAYS	45	99	99	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	3	3
42	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
			MISSING_ELSE
74	1	1
75	1	1
78	1	1
79	1	1
			MISSING_ELSE
83	1	1
84	1	1
87	1	1
88	1	1
			MISSING_ELSE
92	1	1
93	1	1
96	1	1
97	1	1
			MISSING_ELSE
101	1	1
102	1	1
105	1	1
106	1	1
			MISSING_ELSE
111	1	1
112	1	1
113	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
132	1	1
134	1	1
135	1	1
137	1	1
142	1	1
143	1	1
144	1	1
147	1	1
148	1	1
149	1	1
150	1	1
			MISSING_ELSE
154	1	1
155	1	1
156	1	1
159	1	1
160	1	1
161	1	1
162	1	1
			MISSING_ELSE
166	1	1
169	1	1
177	1	1
178	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
200	1	1
202	1	1
203	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T56,T48,T49
1	1	Covered	T28,T37,T31

 LINE       62
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T28
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T7,T8

 LINE       191
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T8

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	19	19	100.00	(Not included in score)
Transitions	54	49	90.74
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	150	Covered	T17
AutoCaptGenCnt	137	Covered	T17
AutoCaptReseedCnt	135	Covered	T17
AutoDispatch	119	Covered	T17
AutoFirstAckWait	113	Covered	T17
AutoLoadIns	65	Covered	T17
AutoSendGenCmd	144	Covered	T17
AutoSendReseedCmd	156	Covered	T17
BootDone	93	Covered	T17
BootGenAckWait	84	Covered	T17
BootInsAckWait	75	Covered	T17
BootLoadGen	79	Covered	T17
BootLoadIns	61	Covered	T17
BootLoadUni	97	Covered	T17
BootPulse	88	Covered	T17
BootUniAckWait	102	Covered	T17
Error	178	Covered	T17
Idle	106	Covered	T17
SWPortMode	70	Covered	T17

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	125	Covered	T17
AutoAckWait->Error	178	Covered	T17
AutoAckWait->Idle	200	Covered	T17
AutoCaptGenCnt->AutoSendGenCmd	144	Covered	T17
AutoCaptGenCnt->Error	178	Covered	T17
AutoCaptGenCnt->Idle	200	Covered	T17
AutoCaptReseedCnt->AutoSendReseedCmd	156	Covered	T17
AutoCaptReseedCnt->Error	178	Not Covered
AutoCaptReseedCnt->Idle	200	Covered	T17
AutoDispatch->AutoCaptGenCnt	137	Covered	T17
AutoDispatch->AutoCaptReseedCnt	135	Covered	T17
AutoDispatch->Error	178	Covered	T17
AutoDispatch->Idle	132	Covered	T17
AutoFirstAckWait->AutoDispatch	119	Covered	T17
AutoFirstAckWait->Error	178	Covered	T17
AutoFirstAckWait->Idle	200	Covered	T17
AutoLoadIns->AutoFirstAckWait	113	Covered	T17
AutoLoadIns->Error	178	Covered	T17
AutoLoadIns->Idle	200	Covered	T17
AutoSendGenCmd->AutoAckWait	150	Covered	T17
AutoSendGenCmd->Error	178	Covered	T17
AutoSendGenCmd->Idle	200	Covered	T17
AutoSendReseedCmd->AutoAckWait	162	Covered	T17
AutoSendReseedCmd->Error	178	Covered	T17
AutoSendReseedCmd->Idle	200	Not Covered
BootDone->BootLoadUni	97	Covered	T17
BootDone->Error	178	Covered	T17
BootDone->Idle	200	Covered	T17
BootGenAckWait->BootPulse	88	Covered	T17
BootGenAckWait->Error	178	Covered	T17
BootGenAckWait->Idle	200	Covered	T17
BootInsAckWait->BootLoadGen	79	Covered	T17
BootInsAckWait->Error	178	Covered	T17
BootInsAckWait->Idle	200	Covered	T17
BootLoadGen->BootGenAckWait	84	Covered	T17
BootLoadGen->Error	178	Covered	T17
BootLoadGen->Idle	200	Covered	T17
BootLoadIns->BootInsAckWait	75	Covered	T17
BootLoadIns->Error	178	Covered	T17
BootLoadIns->Idle	200	Covered	T17
BootLoadUni->BootUniAckWait	102	Covered	T17
BootLoadUni->Error	178	Not Covered
BootLoadUni->Idle	200	Not Covered
BootPulse->BootDone	93	Covered	T17
BootPulse->Error	178	Covered	T17
BootPulse->Idle	200	Covered	T17
BootUniAckWait->Error	178	Not Covered
BootUniAckWait->Idle	106	Covered	T17
Idle->AutoLoadIns	65	Covered	T17
Idle->BootLoadIns	61	Covered	T17
Idle->Error	178	Covered	T17
Idle->SWPortMode	70	Covered	T17
SWPortMode->Error	178	Covered	T17
SWPortMode->Idle	200	Covered	T17

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		39	39	100.00
IF	40	2	2	100.00
CASE	58	34	34	100.00
IF	177	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	40	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	58	case (state_q)
-2-:	60	if ((boot_req_mode_i && edn_enable_i))
-3-:	62	if ((auto_req_mode_i && edn_enable_i))
-4-:	66	if (edn_enable_i)
-5-:	78	if (csrng_cmd_ack_i)
-6-:	87	if (csrng_cmd_ack_i)
-7-:	96	if ((!boot_req_mode_i))
-8-:	105	if (csrng_cmd_ack_i)
-9-:	112	if (sw_cmd_req_load_i)
-10-:	118	if (csrng_cmd_ack_i)
-11-:	124	if (csrng_cmd_ack_i)
-12-:	130	if ((!auto_req_mode_i))
-13-:	134	if (max_reqs_cnt_zero_i)
-14-:	149	if (cmd_sent_i)
-15-:	161	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T28,T37,T31
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T8
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T28
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T28,T37,T31
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T28,T37,T31
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T28,T37,T31
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T28,T37,T31
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T28,T37,T31
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T28,T37,T31
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T28,T37,T31
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T31,T78
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T37,T56,T48
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T28,T31,T78
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T28,T31,T78
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T28,T31,T78
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T7,T8
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T7,T8
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T7,T8
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T7,T8
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T7,T8,T29
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T7,T8,T29
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T29,T38,T41
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T7,T8,T29
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T2,T7,T8
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T8
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T7,T8
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T2,T7,T8
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T29
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T7,T8,T29
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T7,T8,T29
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T28
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T64

	LineNo.	Expression
-1-:	177	if (local_escalate_i)
-2-:	191	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T7,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	214397798	141243	0	0
FpvSecCmErrorStEscalate_A	214397798	142183	0	0
u_state_regs_A	214361748	214201150	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214397798	141243	0	0
T2	1236	592	0	0
T3	741	348	0	0
T4	30855	9560	0	0
T5	0	617	0	0
T7	2693	0	0	0
T8	3607	0	0	0
T28	2642	0	0	0
T29	3042	0	0	0
T33	3143	0	0	0
T37	997	0	0	0
T47	1005	0	0	0
T48	0	1159	0	0
T49	0	650	0	0
T50	0	654	0	0
T51	0	628	0	0
T58	0	188	0	0
T63	0	378	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214397798	142183	0	0
T2	1236	593	0	0
T3	741	349	0	0
T4	30855	9740	0	0
T5	0	618	0	0
T7	2693	0	0	0
T8	3607	0	0	0
T28	2642	0	0	0
T29	3042	0	0	0
T33	3143	0	0	0
T37	997	0	0	0
T47	1005	0	0	0
T48	0	1160	0	0
T49	0	651	0	0
T50	0	655	0	0
T51	0	629	0	0
T58	0	189	0	0
T63	0	379	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214361748	214201150	0	0
T1	2101	2043	0	0
T2	1049	878	0	0
T3	629	500	0	0
T4	30855	16027	0	0
T7	2693	2615	0	0
T8	3607	3542	0	0
T28	2642	2562	0	0
T29	3042	2975	0	0
T37	997	919	0	0
T47	1005	942	0	0