Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.57	100.00	89.71			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.57	100.00	89.71			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.57	100.00	89.71			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.57	100.00	89.71			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.57	100.00	89.71			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.57	100.00	89.71			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.57	100.00	89.71			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T8

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T17
DataWait	75	Covered	T17
Disabled	107	Covered	T17
EndPointClear	63	Covered	T17
Error	99	Covered	T17
Idle	68	Covered	T17

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T17
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T17
DataWait->AckPls	80	Covered	T17
DataWait->Disabled	107	Covered	T17
DataWait->Error	99	Covered	T17
Disabled->EndPointClear	63	Covered	T17
Disabled->Error	99	Covered	T17
EndPointClear->Disabled	107	Covered	T17
EndPointClear->Error	99	Covered	T17
EndPointClear->Idle	68	Covered	T17
Idle->DataWait	75	Covered	T17
Idle->Disabled	107	Covered	T17
Idle->Error	99	Covered	T17

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T3,T7
Idle	-	1	0	-	Covered	T1,T7,T28
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T3,T7
DataWait	-	-	-	0	Covered	T1,T7,T28
AckPls	-	-	-	-	Covered	T1,T3,T7
Error	-	-	-	-	Covered	T2,T3,T4
default	-	-	-	-	Covered	T4,T58,T63

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T7,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1500784586	1000801	0	0
FpvSecCmErrorStEscalate_A	1500784586	1007381	0	0
u_state_regs_A	1500748536	1499624350	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1500784586	1000801	0	0
T2	8652	4144	0	0
T3	5187	2436	0	0
T4	215985	66920	0	0
T5	0	4319	0	0
T7	18851	0	0	0
T8	25249	0	0	0
T28	18494	0	0	0
T29	21294	0	0	0
T33	22001	0	0	0
T37	6979	0	0	0
T47	7035	0	0	0
T48	0	8113	0	0
T49	0	4550	0	0
T50	0	4578	0	0
T51	0	4396	0	0
T58	0	1266	0	0
T63	0	2596	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1500784586	1007381	0	0
T2	8652	4151	0	0
T3	5187	2443	0	0
T4	215985	68180	0	0
T5	0	4326	0	0
T7	18851	0	0	0
T8	25249	0	0	0
T28	18494	0	0	0
T29	21294	0	0	0
T33	22001	0	0	0
T37	6979	0	0	0
T47	7035	0	0	0
T48	0	8120	0	0
T49	0	4557	0	0
T50	0	4585	0	0
T51	0	4403	0	0
T58	0	1273	0	0
T63	0	2603	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1500748536	1499624350	0	0
T1	14707	14301	0	0
T2	8465	7268	0	0
T3	5075	4172	0	0
T4	215985	112189	0	0
T7	18851	18305	0	0
T8	25249	24794	0	0
T28	18494	17934	0	0
T29	21294	20825	0	0
T37	6979	6433	0	0
T47	7035	6594	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T17
DataWait	75	Covered	T17
Disabled	107	Covered	T17
EndPointClear	63	Covered	T17
Error	99	Covered	T17
Idle	68	Covered	T17

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T17
DataWait->AckPls	80	Covered	T17
DataWait->Disabled	107	Covered	T17
DataWait->Error	99	Covered	T17
Disabled->EndPointClear	63	Covered	T17
Disabled->Error	99	Covered	T17
EndPointClear->Disabled	107	Covered	T17
EndPointClear->Error	99	Covered	T17
EndPointClear->Idle	68	Covered	T17
Idle->DataWait	75	Covered	T17
Idle->Disabled	107	Covered	T17
Idle->Error	99	Covered	T17

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T28,T8
Idle	-	1	0	-	Covered	T1,T28,T8
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T28,T8
DataWait	-	-	-	0	Covered	T1,T28,T8
AckPls	-	-	-	-	Covered	T1,T28,T8
Error	-	-	-	-	Covered	T2,T3,T4
default	-	-	-	-	Covered	T4,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T7,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	214397798	143293	0	0
FpvSecCmErrorStEscalate_A	214397798	144233	0	0
u_state_regs_A	214397798	214237200	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214397798	143293	0	0
T2	1236	592	0	0
T3	741	348	0	0
T4	30855	9560	0	0
T5	0	617	0	0
T7	2693	0	0	0
T8	3607	0	0	0
T28	2642	0	0	0
T29	3042	0	0	0
T33	3143	0	0	0
T37	997	0	0	0
T47	1005	0	0	0
T48	0	1159	0	0
T49	0	650	0	0
T50	0	654	0	0
T51	0	628	0	0
T58	0	188	0	0
T63	0	378	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214397798	144233	0	0
T2	1236	593	0	0
T3	741	349	0	0
T4	30855	9740	0	0
T5	0	618	0	0
T7	2693	0	0	0
T8	3607	0	0	0
T28	2642	0	0	0
T29	3042	0	0	0
T33	3143	0	0	0
T37	997	0	0	0
T47	1005	0	0	0
T48	0	1160	0	0
T49	0	651	0	0
T50	0	655	0	0
T51	0	629	0	0
T58	0	189	0	0
T63	0	379	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214397798	214237200	0	0
T1	2101	2043	0	0
T2	1236	1065	0	0
T3	741	612	0	0
T4	30855	16027	0	0
T7	2693	2615	0	0
T8	3607	3542	0	0
T28	2642	2562	0	0
T29	3042	2975	0	0
T37	997	919	0	0
T47	1005	942	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T17
DataWait	75	Covered	T17
Disabled	107	Covered	T17
EndPointClear	63	Covered	T17
Error	99	Covered	T17
Idle	68	Covered	T17

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T17
DataWait->AckPls	80	Covered	T17
DataWait->Disabled	107	Covered	T17
DataWait->Error	99	Covered	T17
Disabled->EndPointClear	63	Covered	T17
Disabled->Error	99	Covered	T17
EndPointClear->Disabled	107	Covered	T17
EndPointClear->Error	99	Covered	T17
EndPointClear->Idle	68	Covered	T17
Idle->DataWait	75	Covered	T17
Idle->Disabled	107	Covered	T17
Idle->Error	99	Covered	T17

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T3,T29
Idle	-	1	0	-	Covered	T1,T3,T29
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T3,T29
DataWait	-	-	-	0	Covered	T1,T29,T37
AckPls	-	-	-	-	Covered	T1,T3,T29
Error	-	-	-	-	Covered	T2,T3,T4
default	-	-	-	-	Covered	T4,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T7,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	214397798	143293	0	0
FpvSecCmErrorStEscalate_A	214397798	144233	0	0
u_state_regs_A	214397798	214237200	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214397798	143293	0	0
T2	1236	592	0	0
T3	741	348	0	0
T4	30855	9560	0	0
T5	0	617	0	0
T7	2693	0	0	0
T8	3607	0	0	0
T28	2642	0	0	0
T29	3042	0	0	0
T33	3143	0	0	0
T37	997	0	0	0
T47	1005	0	0	0
T48	0	1159	0	0
T49	0	650	0	0
T50	0	654	0	0
T51	0	628	0	0
T58	0	188	0	0
T63	0	378	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214397798	144233	0	0
T2	1236	593	0	0
T3	741	349	0	0
T4	30855	9740	0	0
T5	0	618	0	0
T7	2693	0	0	0
T8	3607	0	0	0
T28	2642	0	0	0
T29	3042	0	0	0
T33	3143	0	0	0
T37	997	0	0	0
T47	1005	0	0	0
T48	0	1160	0	0
T49	0	651	0	0
T50	0	655	0	0
T51	0	629	0	0
T58	0	189	0	0
T63	0	379	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214397798	214237200	0	0
T1	2101	2043	0	0
T2	1236	1065	0	0
T3	741	612	0	0
T4	30855	16027	0	0
T7	2693	2615	0	0
T8	3607	3542	0	0
T28	2642	2562	0	0
T29	3042	2975	0	0
T37	997	919	0	0
T47	1005	942	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T17
DataWait	75	Covered	T17
Disabled	107	Covered	T17
EndPointClear	63	Covered	T17
Error	99	Covered	T17
Idle	68	Covered	T17

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T17
DataWait->AckPls	80	Covered	T17
DataWait->Disabled	107	Covered	T17
DataWait->Error	99	Covered	T17
Disabled->EndPointClear	63	Covered	T17
Disabled->Error	99	Covered	T17
EndPointClear->Disabled	107	Covered	T17
EndPointClear->Error	99	Covered	T17
EndPointClear->Idle	68	Covered	T17
Idle->DataWait	75	Covered	T17
Idle->Disabled	107	Covered	T17
Idle->Error	99	Covered	T17

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T28,T8
Idle	-	1	0	-	Covered	T1,T28,T8
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T28,T8
DataWait	-	-	-	0	Covered	T1,T28,T8
AckPls	-	-	-	-	Covered	T1,T28,T8
Error	-	-	-	-	Covered	T2,T3,T4
default	-	-	-	-	Covered	T4,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T7,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	214397798	143293	0	0
FpvSecCmErrorStEscalate_A	214397798	144233	0	0
u_state_regs_A	214397798	214237200	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214397798	143293	0	0
T2	1236	592	0	0
T3	741	348	0	0
T4	30855	9560	0	0
T5	0	617	0	0
T7	2693	0	0	0
T8	3607	0	0	0
T28	2642	0	0	0
T29	3042	0	0	0
T33	3143	0	0	0
T37	997	0	0	0
T47	1005	0	0	0
T48	0	1159	0	0
T49	0	650	0	0
T50	0	654	0	0
T51	0	628	0	0
T58	0	188	0	0
T63	0	378	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214397798	144233	0	0
T2	1236	593	0	0
T3	741	349	0	0
T4	30855	9740	0	0
T5	0	618	0	0
T7	2693	0	0	0
T8	3607	0	0	0
T28	2642	0	0	0
T29	3042	0	0	0
T33	3143	0	0	0
T37	997	0	0	0
T47	1005	0	0	0
T48	0	1160	0	0
T49	0	651	0	0
T50	0	655	0	0
T51	0	629	0	0
T58	0	189	0	0
T63	0	379	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214397798	214237200	0	0
T1	2101	2043	0	0
T2	1236	1065	0	0
T3	741	612	0	0
T4	30855	16027	0	0
T7	2693	2615	0	0
T8	3607	3542	0	0
T28	2642	2562	0	0
T29	3042	2975	0	0
T37	997	919	0	0
T47	1005	942	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T17
DataWait	75	Covered	T17
Disabled	107	Covered	T17
EndPointClear	63	Covered	T17
Error	99	Covered	T17
Idle	68	Covered	T17

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T17
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T17
DataWait->AckPls	80	Covered	T17
DataWait->Disabled	107	Covered	T17
DataWait->Error	99	Not Covered
Disabled->EndPointClear	63	Covered	T17
Disabled->Error	99	Covered	T17
EndPointClear->Disabled	107	Covered	T17
EndPointClear->Error	99	Covered	T17
EndPointClear->Idle	68	Covered	T17
Idle->DataWait	75	Covered	T17
Idle->Disabled	107	Covered	T17
Idle->Error	99	Covered	T17

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T29,T30
Idle	-	1	0	-	Covered	T1,T29,T30
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T29,T30
DataWait	-	-	-	0	Covered	T1,T29,T30
AckPls	-	-	-	-	Covered	T1,T29,T30
Error	-	-	-	-	Covered	T2,T3,T4
default	-	-	-	-	Covered	T4,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T7,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	214397798	143293	0	0
FpvSecCmErrorStEscalate_A	214397798	144233	0	0
u_state_regs_A	214397798	214237200	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214397798	143293	0	0
T2	1236	592	0	0
T3	741	348	0	0
T4	30855	9560	0	0
T5	0	617	0	0
T7	2693	0	0	0
T8	3607	0	0	0
T28	2642	0	0	0
T29	3042	0	0	0
T33	3143	0	0	0
T37	997	0	0	0
T47	1005	0	0	0
T48	0	1159	0	0
T49	0	650	0	0
T50	0	654	0	0
T51	0	628	0	0
T58	0	188	0	0
T63	0	378	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214397798	144233	0	0
T2	1236	593	0	0
T3	741	349	0	0
T4	30855	9740	0	0
T5	0	618	0	0
T7	2693	0	0	0
T8	3607	0	0	0
T28	2642	0	0	0
T29	3042	0	0	0
T33	3143	0	0	0
T37	997	0	0	0
T47	1005	0	0	0
T48	0	1160	0	0
T49	0	651	0	0
T50	0	655	0	0
T51	0	629	0	0
T58	0	189	0	0
T63	0	379	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214397798	214237200	0	0
T1	2101	2043	0	0
T2	1236	1065	0	0
T3	741	612	0	0
T4	30855	16027	0	0
T7	2693	2615	0	0
T8	3607	3542	0	0
T28	2642	2562	0	0
T29	3042	2975	0	0
T37	997	919	0	0
T47	1005	942	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T17
DataWait	75	Covered	T17
Disabled	107	Covered	T17
EndPointClear	63	Covered	T17
Error	99	Covered	T17
Idle	68	Covered	T17

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T17
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T17
DataWait->AckPls	80	Covered	T17
DataWait->Disabled	107	Covered	T17
DataWait->Error	99	Covered	T17
Disabled->EndPointClear	63	Covered	T17
Disabled->Error	99	Covered	T17
EndPointClear->Disabled	107	Covered	T17
EndPointClear->Error	99	Covered	T17
EndPointClear->Idle	68	Covered	T17
Idle->DataWait	75	Covered	T17
Idle->Disabled	107	Covered	T17
Idle->Error	99	Covered	T17

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T7,T31
Idle	-	1	0	-	Covered	T1,T7,T31
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T7,T31
DataWait	-	-	-	0	Covered	T1,T7,T31
AckPls	-	-	-	-	Covered	T1,T7,T31
Error	-	-	-	-	Covered	T2,T3,T4
default	-	-	-	-	Covered	T4,T58,T63

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T7,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	214397798	141043	0	0
FpvSecCmErrorStEscalate_A	214397798	141983	0	0
u_state_regs_A	214361748	214201150	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214397798	141043	0	0
T2	1236	592	0	0
T3	741	348	0	0
T4	30855	9560	0	0
T5	0	617	0	0
T7	2693	0	0	0
T8	3607	0	0	0
T28	2642	0	0	0
T29	3042	0	0	0
T33	3143	0	0	0
T37	997	0	0	0
T47	1005	0	0	0
T48	0	1159	0	0
T49	0	650	0	0
T50	0	654	0	0
T51	0	628	0	0
T58	0	138	0	0
T63	0	328	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214397798	141983	0	0
T2	1236	593	0	0
T3	741	349	0	0
T4	30855	9740	0	0
T5	0	618	0	0
T7	2693	0	0	0
T8	3607	0	0	0
T28	2642	0	0	0
T29	3042	0	0	0
T33	3143	0	0	0
T37	997	0	0	0
T47	1005	0	0	0
T48	0	1160	0	0
T49	0	651	0	0
T50	0	655	0	0
T51	0	629	0	0
T58	0	139	0	0
T63	0	329	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214361748	214201150	0	0
T1	2101	2043	0	0
T2	1049	878	0	0
T3	629	500	0	0
T4	30855	16027	0	0
T7	2693	2615	0	0
T8	3607	3542	0	0
T28	2642	2562	0	0
T29	3042	2975	0	0
T37	997	919	0	0
T47	1005	942	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T17
DataWait	75	Covered	T17
Disabled	107	Covered	T17
EndPointClear	63	Covered	T17
Error	99	Covered	T17
Idle	68	Covered	T17

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T17
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T17
DataWait->AckPls	80	Covered	T17
DataWait->Disabled	107	Covered	T17
DataWait->Error	99	Covered	T17
Disabled->EndPointClear	63	Covered	T17
Disabled->Error	99	Covered	T17
EndPointClear->Disabled	107	Covered	T17
EndPointClear->Error	99	Covered	T17
EndPointClear->Idle	68	Covered	T17
Idle->DataWait	75	Covered	T17
Idle->Disabled	107	Covered	T17
Idle->Error	99	Covered	T17

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T7,T29
Idle	-	1	0	-	Covered	T1,T7,T29
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T7,T29
DataWait	-	-	-	0	Covered	T1,T7,T29
AckPls	-	-	-	-	Covered	T1,T7,T29
Error	-	-	-	-	Covered	T2,T3,T4
default	-	-	-	-	Covered	T4,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T7,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	214397798	143293	0	0
FpvSecCmErrorStEscalate_A	214397798	144233	0	0
u_state_regs_A	214397798	214237200	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214397798	143293	0	0
T2	1236	592	0	0
T3	741	348	0	0
T4	30855	9560	0	0
T5	0	617	0	0
T7	2693	0	0	0
T8	3607	0	0	0
T28	2642	0	0	0
T29	3042	0	0	0
T33	3143	0	0	0
T37	997	0	0	0
T47	1005	0	0	0
T48	0	1159	0	0
T49	0	650	0	0
T50	0	654	0	0
T51	0	628	0	0
T58	0	188	0	0
T63	0	378	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214397798	144233	0	0
T2	1236	593	0	0
T3	741	349	0	0
T4	30855	9740	0	0
T5	0	618	0	0
T7	2693	0	0	0
T8	3607	0	0	0
T28	2642	0	0	0
T29	3042	0	0	0
T33	3143	0	0	0
T37	997	0	0	0
T47	1005	0	0	0
T48	0	1160	0	0
T49	0	651	0	0
T50	0	655	0	0
T51	0	629	0	0
T58	0	189	0	0
T63	0	379	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214397798	214237200	0	0
T1	2101	2043	0	0
T2	1236	1065	0	0
T3	741	612	0	0
T4	30855	16027	0	0
T7	2693	2615	0	0
T8	3607	3542	0	0
T28	2642	2562	0	0
T29	3042	2975	0	0
T37	997	919	0	0
T47	1005	942	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T17
DataWait	75	Covered	T17
Disabled	107	Covered	T17
EndPointClear	63	Covered	T17
Error	99	Covered	T17
Idle	68	Covered	T17

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T17
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T17
DataWait->AckPls	80	Covered	T17
DataWait->Disabled	107	Covered	T17
DataWait->Error	99	Covered	T17
Disabled->EndPointClear	63	Covered	T17
Disabled->Error	99	Covered	T17
EndPointClear->Disabled	107	Covered	T17
EndPointClear->Error	99	Covered	T17
EndPointClear->Idle	68	Covered	T17
Idle->DataWait	75	Covered	T17
Idle->Disabled	107	Covered	T17
Idle->Error	99	Covered	T17

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T28,T33
Idle	-	1	0	-	Covered	T1,T2,T28
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T28,T33
DataWait	-	-	-	0	Covered	T1,T2,T28
AckPls	-	-	-	-	Covered	T1,T28,T33
Error	-	-	-	-	Covered	T2,T3,T4
default	-	-	-	-	Covered	T4,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T7,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	214397798	143293	0	0
FpvSecCmErrorStEscalate_A	214397798	144233	0	0
u_state_regs_A	214397798	214237200	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214397798	143293	0	0
T2	1236	592	0	0
T3	741	348	0	0
T4	30855	9560	0	0
T5	0	617	0	0
T7	2693	0	0	0
T8	3607	0	0	0
T28	2642	0	0	0
T29	3042	0	0	0
T33	3143	0	0	0
T37	997	0	0	0
T47	1005	0	0	0
T48	0	1159	0	0
T49	0	650	0	0
T50	0	654	0	0
T51	0	628	0	0
T58	0	188	0	0
T63	0	378	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214397798	144233	0	0
T2	1236	593	0	0
T3	741	349	0	0
T4	30855	9740	0	0
T5	0	618	0	0
T7	2693	0	0	0
T8	3607	0	0	0
T28	2642	0	0	0
T29	3042	0	0	0
T33	3143	0	0	0
T37	997	0	0	0
T47	1005	0	0	0
T48	0	1160	0	0
T49	0	651	0	0
T50	0	655	0	0
T51	0	629	0	0
T58	0	189	0	0
T63	0	379	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214397798	214237200	0	0
T1	2101	2043	0	0
T2	1236	1065	0	0
T3	741	612	0	0
T4	30855	16027	0	0
T7	2693	2615	0	0
T8	3607	3542	0	0
T28	2642	2562	0	0
T29	3042	2975	0	0
T37	997	919	0	0
T47	1005	942	0	0