Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	210007070	9450238	0	0
boot_gen_cmd_rd_A	210007070	50046	0	0
boot_ins_cmd_rd_A	210007070	56914	0	0
ctrl_rd_A	210007070	50559	0	0
err_code_test_rd_A	210007070	56718	0	0
intr_enable_rd_A	210007070	55954	0	0
max_num_reqs_between_reseeds_rd_A	210007070	50480	0	0
regwen_rd_A	210007070	57462	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210007070	9450238	0	0
T10	3119	0	0	0
T11	2574	0	0	0
T15	2282	0	0	0
T17	2269	0	0	0
T22	856	0	0	0
T25	498697	183239	0	0
T26	0	162488	0	0
T27	0	329510	0	0
T40	886	0	0	0
T64	915	0	0	0
T129	996	0	0	0
T140	1412	0	0	0
T146	0	110494	0	0
T148	0	460449	0	0
T159	0	132596	0	0
T187	0	188890	0	0
T188	0	272562	0	0
T189	0	314475	0	0
T190	0	117718	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210007070	50046	0	0
T10	3119	0	0	0
T11	2574	0	0	0
T15	2282	0	0	0
T17	2269	0	0	0
T22	856	0	0	0
T25	498697	2852	0	0
T40	886	0	0	0
T60	0	2379	0	0
T63	0	7446	0	0
T64	915	0	0	0
T129	996	0	0	0
T140	1412	0	0	0
T163	0	3470	0	0
T187	0	2922	0	0
T190	0	3505	0	0
T191	0	1116	0	0
T192	0	3948	0	0
T193	0	1622	0	0
T194	0	4035	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210007070	56914	0	0
T10	3119	0	0	0
T11	2574	0	0	0
T15	2282	0	0	0
T17	2269	0	0	0
T22	856	0	0	0
T25	498697	3217	0	0
T40	886	0	0	0
T60	0	2563	0	0
T63	0	8366	0	0
T64	915	0	0	0
T129	996	0	0	0
T140	1412	0	0	0
T163	0	4094	0	0
T187	0	3539	0	0
T190	0	3850	0	0
T191	0	1122	0	0
T192	0	4767	0	0
T193	0	2089	0	0
T194	0	4653	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210007070	50559	0	0
T9	7221	0	0	0
T10	3119	0	0	0
T11	2574	0	0	0
T22	856	0	0	0
T25	498697	2762	0	0
T29	2309	6	0	0
T60	0	2427	0	0
T63	0	7831	0	0
T64	915	0	0	0
T129	996	0	0	0
T139	1303	0	0	0
T140	1412	0	0	0
T187	0	2650	0	0
T190	0	3478	0	0
T191	0	1204	0	0
T192	0	4086	0	0
T195	0	8	0	0
T196	0	4	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210007070	56718	0	0
T10	3119	0	0	0
T11	2574	0	0	0
T15	2282	0	0	0
T17	2269	0	0	0
T22	856	0	0	0
T25	498697	3073	0	0
T40	886	0	0	0
T60	0	2617	0	0
T63	0	8469	0	0
T64	915	0	0	0
T129	996	0	0	0
T140	1412	0	0	0
T163	0	4305	0	0
T187	0	3484	0	0
T190	0	3817	0	0
T191	0	1102	0	0
T192	0	4779	0	0
T193	0	2125	0	0
T194	0	4600	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210007070	55954	0	0
T10	3119	0	0	0
T11	2574	0	0	0
T15	2282	0	0	0
T17	2269	0	0	0
T22	856	0	0	0
T25	498697	3264	0	0
T40	886	0	0	0
T60	0	2191	0	0
T63	0	7905	0	0
T64	915	0	0	0
T129	996	0	0	0
T140	1412	0	0	0
T187	0	3139	0	0
T190	0	3798	0	0
T191	0	1321	0	0
T192	0	4568	0	0
T197	0	48	0	0
T198	0	6	0	0
T199	0	80	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210007070	50480	0	0
T10	3119	0	0	0
T11	2574	0	0	0
T15	2282	0	0	0
T17	2269	0	0	0
T22	856	0	0	0
T25	498697	2915	0	0
T40	886	0	0	0
T60	0	2246	0	0
T63	0	7279	0	0
T64	915	0	0	0
T129	996	0	0	0
T140	1412	0	0	0
T163	0	3857	0	0
T187	0	2642	0	0
T190	0	3412	0	0
T191	0	920	0	0
T192	0	4049	0	0
T193	0	1851	0	0
T194	0	4186	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210007070	57462	0	0
T10	3119	0	0	0
T11	2574	0	0	0
T15	2282	0	0	0
T17	2269	0	0	0
T22	856	0	0	0
T25	498697	3258	0	0
T40	886	0	0	0
T60	0	2457	0	0
T63	0	8349	0	0
T64	915	0	0	0
T129	996	0	0	0
T140	1412	0	0	0
T163	0	4201	0	0
T187	0	3391	0	0
T190	0	3865	0	0
T191	0	1117	0	0
T192	0	4734	0	0
T193	0	2116	0	0
T194	0	4565	0	0