Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	198644817	8247627	0	0
boot_gen_cmd_rd_A	198644817	79838	0	0
boot_ins_cmd_rd_A	198644817	90012	0	0
ctrl_rd_A	198644817	80500	0	0
err_code_test_rd_A	198644817	90884	0	0
intr_enable_rd_A	198644817	87396	0	0
max_num_reqs_between_reseeds_rd_A	198644817	80207	0	0
regwen_rd_A	198644817	93184	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198644817	8247627	0	0
T18	2392	0	0	0
T19	2389	0	0	0
T25	121557	44468	0	0
T26	0	250459	0	0
T27	0	117805	0	0
T44	1121	0	0	0
T52	10663	0	0	0
T53	1560	0	0	0
T54	3290	0	0	0
T60	829	0	0	0
T136	0	138228	0	0
T137	0	163602	0	0
T140	1705	0	0	0
T142	0	112726	0	0
T143	0	65873	0	0
T145	1240	0	0	0
T186	0	114337	0	0
T187	0	246175	0	0
T188	0	242881	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198644817	79838	0	0
T18	2392	0	0	0
T19	2389	0	0	0
T25	121557	1133	0	0
T26	0	7559	0	0
T44	1121	0	0	0
T52	10663	0	0	0
T53	1560	0	0	0
T54	3290	0	0	0
T60	829	0	0	0
T140	1705	0	0	0
T143	0	2069	0	0
T145	1240	0	0	0
T186	0	1568	0	0
T189	0	4095	0	0
T190	0	1296	0	0
T191	0	2841	0	0
T192	0	7552	0	0
T193	0	931	0	0
T194	0	12415	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198644817	90012	0	0
T18	2392	0	0	0
T19	2389	0	0	0
T25	121557	1442	0	0
T26	0	8194	0	0
T44	1121	0	0	0
T52	10663	0	0	0
T53	1560	0	0	0
T54	3290	0	0	0
T60	829	0	0	0
T140	1705	0	0	0
T143	0	2184	0	0
T145	1240	0	0	0
T186	0	1900	0	0
T189	0	4844	0	0
T190	0	1572	0	0
T191	0	3191	0	0
T192	0	8157	0	0
T193	0	1063	0	0
T194	0	14051	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198644817	80500	0	0
T18	2392	0	0	0
T19	2389	0	0	0
T25	121557	1469	0	0
T26	0	7678	0	0
T44	1121	0	0	0
T45	0	5	0	0
T52	10663	0	0	0
T53	1560	0	0	0
T54	3290	0	0	0
T60	829	0	0	0
T119	0	3	0	0
T125	0	5	0	0
T140	1705	0	0	0
T143	0	2084	0	0
T145	1240	0	0	0
T186	0	1767	0	0
T189	0	4329	0	0
T190	0	1178	0	0
T195	0	1	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198644817	90884	0	0
T18	2392	0	0	0
T19	2389	0	0	0
T25	121557	1446	0	0
T26	0	8321	0	0
T44	1121	0	0	0
T52	10663	0	0	0
T53	1560	0	0	0
T54	3290	0	0	0
T60	829	0	0	0
T140	1705	0	0	0
T143	0	2197	0	0
T145	1240	0	0	0
T186	0	2045	0	0
T189	0	4800	0	0
T190	0	1618	0	0
T191	0	3354	0	0
T192	0	8305	0	0
T193	0	1065	0	0
T194	0	14326	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198644817	87396	0	0
T18	2392	0	0	0
T19	2389	0	0	0
T25	121557	1476	0	0
T26	0	7788	0	0
T44	1121	0	0	0
T52	10663	0	0	0
T53	1560	0	0	0
T54	3290	0	0	0
T60	829	0	0	0
T140	1705	0	0	0
T143	0	2191	0	0
T145	1240	0	0	0
T186	0	1786	0	0
T189	0	4695	0	0
T190	0	1486	0	0
T191	0	3012	0	0
T192	0	7517	0	0
T193	0	1102	0	0
T196	0	73	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198644817	80207	0	0
T18	2392	0	0	0
T19	2389	0	0	0
T25	121557	1353	0	0
T26	0	7438	0	0
T44	1121	0	0	0
T52	10663	0	0	0
T53	1560	0	0	0
T54	3290	0	0	0
T60	829	0	0	0
T140	1705	0	0	0
T143	0	2083	0	0
T145	1240	0	0	0
T186	0	1835	0	0
T189	0	4181	0	0
T190	0	1221	0	0
T191	0	3131	0	0
T192	0	7099	0	0
T193	0	860	0	0
T194	0	12389	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198644817	93184	0	0
T18	2392	0	0	0
T19	2389	0	0	0
T25	121557	1593	0	0
T26	0	8640	0	0
T44	1121	0	0	0
T52	10663	0	0	0
T53	1560	0	0	0
T54	3290	0	0	0
T60	829	0	0	0
T140	1705	0	0	0
T143	0	2322	0	0
T145	1240	0	0	0
T186	0	1926	0	0
T189	0	4698	0	0
T190	0	1854	0	0
T191	0	3571	0	0
T192	0	8202	0	0
T193	0	1197	0	0
T194	0	14488	0	0