Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.52	98.24	93.82	97.01	81.50	96.76	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.47	99.92	92.48	82.54	81.50	99.52	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T24,T25,T26

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T2,T4

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1170	1170	100.00
Total Bits 0->1	585	585	100.00
Total Bits 1->0	585	585	100.00

Ports	69	69	100.00
Port Bits	1170	1170	100.00
Port Bits 0->1	585	585	100.00
Port Bits 1->0	585	585	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T18,T8	Yes	T1,T18,T8	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T18,T13	Yes	T1,T18,T13	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T34,T35,T36	Yes	T34,T35,T36	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T18	Yes	T3,T4,T18	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T18,T19	Yes	T1,T18,T19	INPUT
edn_i[1].edn_req	Yes	Yes	T3,T8,T37	Yes	T3,T8,T37	INPUT
edn_i[2].edn_req	Yes	Yes	T38,T10,T39	Yes	T38,T10,T39	INPUT
edn_i[3].edn_req	Yes	Yes	T4,T10,T40	Yes	T4,T10,T40	INPUT
edn_i[4].edn_req	Yes	Yes	T2,T38,T10	Yes	T2,T38,T10	INPUT
edn_i[5].edn_req	Yes	Yes	T40,T39,T41	Yes	T40,T39,T41	INPUT
edn_i[6].edn_req	Yes	Yes	T3,T14,T24	Yes	T3,T14,T24	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T3,T37,T38	Yes	T3,T37,T38	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T37,T38,T42	Yes	T3,T37,T38	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T3,T8,T37	Yes	T3,T8,T37	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T38,T10,T39	Yes	T38,T10,T39	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T38,T10,T39	Yes	T38,T10,T39	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T38,T10,T39	Yes	T38,T10,T39	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T10,T40,T41	Yes	T10,T40,T39	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T10,T40,T43	Yes	T10,T40,T39	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T4,T10,T40	Yes	T4,T10,T40	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T38,T10,T39	Yes	T38,T10,T39	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T38,T39,T44	Yes	T38,T10,T39	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T38,T10,T39	Yes	T38,T10,T39	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T40,T39,T41	Yes	T40,T39,T41	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T39,T41,T28	Yes	T40,T39,T41	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T40,T39,T41	Yes	T40,T39,T41	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T24,T40,T45	Yes	T3,T24,T40	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T41,T46,T11	Yes	T3,T40,T45	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T3,T24,T40	Yes	T3,T24,T40	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T3,T4,T18	Yes	T3,T4,T18	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T3,T4,T18	Yes	T3,T4,T18	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T3,T18,T19	Yes	T3,T18,T19	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T3,T18,T19	Yes	T3,T18,T19	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T3,T4,T18	Yes	T3,T4,T18	INPUT
csrng_cmd_i.csrng_rsp_sts[1:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T3,T4,T18	Yes	T3,T4,T18	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T47,T48,T49	Yes	T47,T48,T49	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T50,T51	Yes	T4,T50,T51	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	227365895	227198914	0	0
CsrngAppIfOut_A	227365895	227198914	0	0
FpvSecCmCntAlertCheck_A	227365895	116	0	0
FpvSecCmGenCmdFifoRptrCheck_A	227365895	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	227365895	70	0	0
FpvSecCmMainFsmCheck_A	227365895	70	0	0
FpvSecCmRegWeOnehotCheck_A	227365895	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	227365895	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	227365895	70	0	0
IntrEdnCmdReqDoneKnownO_A	227365895	227198914	0	0
TlAReadyKnownO_A	227365895	227198914	0	0
TlDValidKnownO_A	227365895	227198914	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	227365895	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	227365895	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	227365895	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	227365895	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	227365895	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	227365895	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	227365895	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	227365895	553384	0	304
gen_edn_if_asserts[0].EdnDataStable_A	227365895	24932	0	348
gen_edn_if_asserts[0].EdnEndPointOut_A	227365895	227198914	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	227365895	152078	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	227365895	553384	0	304
gen_edn_if_asserts[1].EdnDataStable_A	227365895	5432	0	118
gen_edn_if_asserts[1].EdnEndPointOut_A	227365895	227198914	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	227365895	152078	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	227365895	553384	0	304
gen_edn_if_asserts[2].EdnDataStable_A	227365895	5175	0	103
gen_edn_if_asserts[2].EdnEndPointOut_A	227365895	227198914	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	227365895	152078	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	227365895	553384	0	304
gen_edn_if_asserts[3].EdnDataStable_A	227365895	4174	0	102
gen_edn_if_asserts[3].EdnEndPointOut_A	227365895	227198914	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	227365895	152078	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	227365895	553384	0	304
gen_edn_if_asserts[4].EdnDataStable_A	227365895	4134	0	106
gen_edn_if_asserts[4].EdnEndPointOut_A	227365895	227198914	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	227365895	152078	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	227365895	553384	0	304
gen_edn_if_asserts[5].EdnDataStable_A	227365895	2810	0	77
gen_edn_if_asserts[5].EdnEndPointOut_A	227365895	227198914	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	227365895	152078	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	227365895	553384	0	304
gen_edn_if_asserts[6].EdnDataStable_A	227365895	1101	0	75
gen_edn_if_asserts[6].EdnEndPointOut_A	227365895	227198914	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	227365895	152078	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	227198914	0	0
T1	551	386	0	0
T2	1030	868	0	0
T3	4425	4374	0	0
T4	898	744	0	0
T8	3575	3506	0	0
T13	2806	2624	0	0
T14	1925	1802	0	0
T18	3595	3517	0	0
T19	2001	1904	0	0
T20	3216	3135	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	227198914	0	0
T1	551	386	0	0
T2	1030	868	0	0
T3	4425	4374	0	0
T4	898	744	0	0
T8	3575	3506	0	0
T13	2806	2624	0	0
T14	1925	1802	0	0
T18	3595	3517	0	0
T19	2001	1904	0	0
T20	3216	3135	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	116	0	0
T4	898	1	0	0
T5	0	1	0	0
T6	0	1	0	0
T7	0	1	0	0
T8	3575	0	0	0
T13	2806	1	0	0
T14	1925	1	0	0
T18	3595	0	0	0
T19	2001	0	0	0
T20	3216	0	0	0
T21	1417	0	0	0
T43	0	1	0	0
T50	2059	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	1716	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	70	0	0
T15	23497	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T55	0	20	0	0
T56	0	10	0	0
T57	2043	0	0	0
T58	101454	0	0	0
T59	1903	0	0	0
T60	1103	0	0	0
T61	2177	0	0	0
T62	1704	0	0	0
T63	14142	0	0	0
T64	676	0	0	0
T65	886	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	70	0	0
T15	23497	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T55	0	20	0	0
T56	0	10	0	0
T57	2043	0	0	0
T58	101454	0	0	0
T59	1903	0	0	0
T60	1103	0	0	0
T61	2177	0	0	0
T62	1704	0	0	0
T63	14142	0	0	0
T64	676	0	0	0
T65	886	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	70	0	0
T15	23497	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T55	0	20	0	0
T56	0	10	0	0
T57	2043	0	0	0
T58	101454	0	0	0
T59	1903	0	0	0
T60	1103	0	0	0
T61	2177	0	0	0
T62	1704	0	0	0
T63	14142	0	0	0
T64	676	0	0	0
T65	886	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	70	0	0
T15	23497	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T55	0	20	0	0
T56	0	10	0	0
T57	2043	0	0	0
T58	101454	0	0	0
T59	1903	0	0	0
T60	1103	0	0	0
T61	2177	0	0	0
T62	1704	0	0	0
T63	14142	0	0	0
T64	676	0	0	0
T65	886	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	70	0	0
T15	23497	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T55	0	20	0	0
T56	0	10	0	0
T57	2043	0	0	0
T58	101454	0	0	0
T59	1903	0	0	0
T60	1103	0	0	0
T61	2177	0	0	0
T62	1704	0	0	0
T63	14142	0	0	0
T64	676	0	0	0
T65	886	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	70	0	0
T15	23497	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T55	0	20	0	0
T56	0	10	0	0
T57	2043	0	0	0
T58	101454	0	0	0
T59	1903	0	0	0
T60	1103	0	0	0
T61	2177	0	0	0
T62	1704	0	0	0
T63	14142	0	0	0
T64	676	0	0	0
T65	886	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	227198914	0	0
T1	551	386	0	0
T2	1030	868	0	0
T3	4425	4374	0	0
T4	898	744	0	0
T8	3575	3506	0	0
T13	2806	2624	0	0
T14	1925	1802	0	0
T18	3595	3517	0	0
T19	2001	1904	0	0
T20	3216	3135	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	227198914	0	0
T1	551	386	0	0
T2	1030	868	0	0
T3	4425	4374	0	0
T4	898	744	0	0
T8	3575	3506	0	0
T13	2806	2624	0	0
T14	1925	1802	0	0
T18	3595	3517	0	0
T19	2001	1904	0	0
T20	3216	3135	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	227198914	0	0
T1	551	386	0	0
T2	1030	868	0	0
T3	4425	4374	0	0
T4	898	744	0	0
T8	3575	3506	0	0
T13	2806	2624	0	0
T14	1925	1802	0	0
T18	3595	3517	0	0
T19	2001	1904	0	0
T20	3216	3135	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	70	0	0
T15	23497	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T55	0	20	0	0
T56	0	10	0	0
T57	2043	0	0	0
T58	101454	0	0	0
T59	1903	0	0	0
T60	1103	0	0	0
T61	2177	0	0	0
T62	1704	0	0	0
T63	14142	0	0	0
T64	676	0	0	0
T65	886	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	70	0	0
T15	23497	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T55	0	20	0	0
T56	0	10	0	0
T57	2043	0	0	0
T58	101454	0	0	0
T59	1903	0	0	0
T60	1103	0	0	0
T61	2177	0	0	0
T62	1704	0	0	0
T63	14142	0	0	0
T64	676	0	0	0
T65	886	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	70	0	0
T15	23497	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T55	0	20	0	0
T56	0	10	0	0
T57	2043	0	0	0
T58	101454	0	0	0
T59	1903	0	0	0
T60	1103	0	0	0
T61	2177	0	0	0
T62	1704	0	0	0
T63	14142	0	0	0
T64	676	0	0	0
T65	886	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	70	0	0
T15	23497	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T55	0	20	0	0
T56	0	10	0	0
T57	2043	0	0	0
T58	101454	0	0	0
T59	1903	0	0	0
T60	1103	0	0	0
T61	2177	0	0	0
T62	1704	0	0	0
T63	14142	0	0	0
T64	676	0	0	0
T65	886	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	70	0	0
T15	23497	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T55	0	20	0	0
T56	0	10	0	0
T57	2043	0	0	0
T58	101454	0	0	0
T59	1903	0	0	0
T60	1103	0	0	0
T61	2177	0	0	0
T62	1704	0	0	0
T63	14142	0	0	0
T64	676	0	0	0
T65	886	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	70	0	0
T15	23497	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T55	0	20	0	0
T56	0	10	0	0
T57	2043	0	0	0
T58	101454	0	0	0
T59	1903	0	0	0
T60	1103	0	0	0
T61	2177	0	0	0
T62	1704	0	0	0
T63	14142	0	0	0
T64	676	0	0	0
T65	886	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	70	0	0
T15	23497	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T55	0	20	0	0
T56	0	10	0	0
T57	2043	0	0	0
T58	101454	0	0	0
T59	1903	0	0	0
T60	1103	0	0	0
T61	2177	0	0	0
T62	1704	0	0	0
T63	14142	0	0	0
T64	676	0	0	0
T65	886	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	553384	0	304
T1	551	186	0	0
T2	1030	511	0	0
T3	4425	1624	0	2
T4	898	247	0	0
T8	3575	1031	0	2
T13	2806	1027	0	0
T14	1925	1132	0	0
T18	3595	18	0	0
T19	2001	15	0	0
T20	3216	70	0	0
T34	0	0	0	2
T35	0	0	0	2
T45	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	24932	0	348
T8	3575	4	0	0
T9	0	0	0	1
T13	2806	0	0	0
T14	1925	0	0	0
T18	3595	50	0	1
T19	2001	41	0	1
T20	3216	19	0	1
T21	1417	3	0	1
T37	0	7	0	1
T50	2059	1	0	0
T54	1716	3	0	1
T71	1450	3	0	1
T72	0	3	0	1
T73	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	227198914	0	0
T1	551	386	0	0
T2	1030	868	0	0
T3	4425	4374	0	0
T4	898	744	0	0
T8	3575	3506	0	0
T13	2806	2624	0	0
T14	1925	1802	0	0
T18	3595	3517	0	0
T19	2001	1904	0	0
T20	3216	3135	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	152078	0	0
T1	551	272	0	0
T2	1030	592	0	0
T3	4425	0	0	0
T4	898	319	0	0
T8	3575	0	0	0
T13	2806	1084	0	0
T14	1925	1165	0	0
T18	3595	0	0	0
T19	2001	0	0	0
T20	3216	0	0	0
T28	0	33	0	0
T50	0	1100	0	0
T51	0	642	0	0
T74	0	1132	0	0
T75	0	642	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	553384	0	304
T1	551	186	0	0
T2	1030	511	0	0
T3	4425	1624	0	2
T4	898	247	0	0
T8	3575	1031	0	2
T13	2806	1027	0	0
T14	1925	1132	0	0
T18	3595	18	0	0
T19	2001	15	0	0
T20	3216	70	0	0
T34	0	0	0	2
T35	0	0	0	2
T45	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	5432	0	118
T3	4425	4	0	0
T4	898	0	0	0
T8	3575	1	0	0
T10	0	3	0	1
T13	2806	0	0	0
T14	1925	0	0	0
T18	3595	0	0	0
T19	2001	0	0	0
T20	3216	0	0	0
T24	0	4	0	1
T37	0	29	0	1
T38	0	60	0	1
T39	0	33	0	1
T41	0	3	0	1
T42	0	7	0	1
T50	2059	0	0	0
T54	1716	0	0	0
T76	0	4	0	1
T77	0	0	0	1
T78	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	227198914	0	0
T1	551	386	0	0
T2	1030	868	0	0
T3	4425	4374	0	0
T4	898	744	0	0
T8	3575	3506	0	0
T13	2806	2624	0	0
T14	1925	1802	0	0
T18	3595	3517	0	0
T19	2001	1904	0	0
T20	3216	3135	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	152078	0	0
T1	551	272	0	0
T2	1030	592	0	0
T3	4425	0	0	0
T4	898	319	0	0
T8	3575	0	0	0
T13	2806	1084	0	0
T14	1925	1165	0	0
T18	3595	0	0	0
T19	2001	0	0	0
T20	3216	0	0	0
T28	0	33	0	0
T50	0	1100	0	0
T51	0	642	0	0
T74	0	1132	0	0
T75	0	642	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	553384	0	304
T1	551	186	0	0
T2	1030	511	0	0
T3	4425	1624	0	2
T4	898	247	0	0
T8	3575	1031	0	2
T13	2806	1027	0	0
T14	1925	1132	0	0
T18	3595	18	0	0
T19	2001	15	0	0
T20	3216	70	0	0
T34	0	0	0	2
T35	0	0	0	2
T45	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	5175	0	103
T10	3742	38	0	1
T22	1263	0	0	0
T24	2486	0	0	0
T38	2609	4	0	1
T39	0	39	0	1
T40	1625	0	0	0
T41	0	3	0	1
T42	2369	0	0	0
T45	3207	0	0	0
T76	0	827	0	1
T77	0	45	0	1
T79	0	3	0	1
T80	0	3	0	1
T81	0	3	0	1
T82	0	11	0	1
T83	3440	0	0	0
T84	2283	0	0	0
T85	8056	0	0	0

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	227198914	0	0
T1	551	386	0	0
T2	1030	868	0	0
T3	4425	4374	0	0
T4	898	744	0	0
T8	3575	3506	0	0
T13	2806	2624	0	0
T14	1925	1802	0	0
T18	3595	3517	0	0
T19	2001	1904	0	0
T20	3216	3135	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	152078	0	0
T1	551	272	0	0
T2	1030	592	0	0
T3	4425	0	0	0
T4	898	319	0	0
T8	3575	0	0	0
T13	2806	1084	0	0
T14	1925	1165	0	0
T18	3595	0	0	0
T19	2001	0	0	0
T20	3216	0	0	0
T28	0	33	0	0
T50	0	1100	0	0
T51	0	642	0	0
T74	0	1132	0	0
T75	0	642	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	553384	0	304
T1	551	186	0	0
T2	1030	511	0	0
T3	4425	1624	0	2
T4	898	247	0	0
T8	3575	1031	0	2
T13	2806	1027	0	0
T14	1925	1132	0	0
T18	3595	18	0	0
T19	2001	15	0	0
T20	3216	70	0	0
T34	0	0	0	2
T35	0	0	0	2
T45	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	4174	0	102
T4	898	1	0	0
T8	3575	0	0	0
T10	0	12	0	1
T13	2806	0	0	0
T14	1925	0	0	0
T18	3595	0	0	0
T19	2001	0	0	0
T20	3216	0	0	0
T21	1417	0	0	0
T39	0	3	0	1
T40	0	8	0	1
T41	0	3	0	1
T43	0	1	0	0
T50	2059	0	0	0
T54	1716	0	0	0
T76	0	3	0	1
T77	0	7	0	1
T86	0	3	0	1
T87	0	27	0	1
T88	0	0	0	1
T89	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	227198914	0	0
T1	551	386	0	0
T2	1030	868	0	0
T3	4425	4374	0	0
T4	898	744	0	0
T8	3575	3506	0	0
T13	2806	2624	0	0
T14	1925	1802	0	0
T18	3595	3517	0	0
T19	2001	1904	0	0
T20	3216	3135	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	152078	0	0
T1	551	272	0	0
T2	1030	592	0	0
T3	4425	0	0	0
T4	898	319	0	0
T8	3575	0	0	0
T13	2806	1084	0	0
T14	1925	1165	0	0
T18	3595	0	0	0
T19	2001	0	0	0
T20	3216	0	0	0
T28	0	33	0	0
T50	0	1100	0	0
T51	0	642	0	0
T74	0	1132	0	0
T75	0	642	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	553384	0	304
T1	551	186	0	0
T2	1030	511	0	0
T3	4425	1624	0	2
T4	898	247	0	0
T8	3575	1031	0	2
T13	2806	1027	0	0
T14	1925	1132	0	0
T18	3595	18	0	0
T19	2001	15	0	0
T20	3216	70	0	0
T34	0	0	0	2
T35	0	0	0	2
T45	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	4134	0	106
T10	3742	15	0	1
T22	1263	0	0	0
T24	2486	0	0	0
T38	2609	47	0	1
T39	0	23	0	1
T40	1625	0	0	0
T41	0	3	0	1
T42	2369	0	0	0
T44	0	49	0	1
T45	3207	0	0	0
T76	0	22	0	1
T77	0	3	0	1
T79	0	3	0	1
T80	0	3	0	1
T83	3440	0	0	0
T84	2283	0	0	0
T85	8056	0	0	0
T86	0	19	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	227198914	0	0
T1	551	386	0	0
T2	1030	868	0	0
T3	4425	4374	0	0
T4	898	744	0	0
T8	3575	3506	0	0
T13	2806	2624	0	0
T14	1925	1802	0	0
T18	3595	3517	0	0
T19	2001	1904	0	0
T20	3216	3135	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	152078	0	0
T1	551	272	0	0
T2	1030	592	0	0
T3	4425	0	0	0
T4	898	319	0	0
T8	3575	0	0	0
T13	2806	1084	0	0
T14	1925	1165	0	0
T18	3595	0	0	0
T19	2001	0	0	0
T20	3216	0	0	0
T28	0	33	0	0
T50	0	1100	0	0
T51	0	642	0	0
T74	0	1132	0	0
T75	0	642	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	553384	0	304
T1	551	186	0	0
T2	1030	511	0	0
T3	4425	1624	0	2
T4	898	247	0	0
T8	3575	1031	0	2
T13	2806	1027	0	0
T14	1925	1132	0	0
T18	3595	18	0	0
T19	2001	15	0	0
T20	3216	70	0	0
T34	0	0	0	2
T35	0	0	0	2
T45	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	2810	0	77
T25	1770	0	0	0
T26	2346	0	0	0
T28	0	1	0	0
T39	2039	15	0	1
T40	1625	3	0	1
T41	0	435	0	1
T44	2623	0	0	0
T45	3207	0	0	0
T51	1341	0	0	0
T75	1247	0	0	0
T76	0	59	0	1
T79	0	3	0	1
T80	0	56	0	1
T81	0	23	0	1
T82	0	0	0	1
T85	8056	0	0	0
T90	0	3	0	1
T91	0	4	0	1
T92	8202	0	0	0

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	227198914	0	0
T1	551	386	0	0
T2	1030	868	0	0
T3	4425	4374	0	0
T4	898	744	0	0
T8	3575	3506	0	0
T13	2806	2624	0	0
T14	1925	1802	0	0
T18	3595	3517	0	0
T19	2001	1904	0	0
T20	3216	3135	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	152078	0	0
T1	551	272	0	0
T2	1030	592	0	0
T3	4425	0	0	0
T4	898	319	0	0
T8	3575	0	0	0
T13	2806	1084	0	0
T14	1925	1165	0	0
T18	3595	0	0	0
T19	2001	0	0	0
T20	3216	0	0	0
T28	0	33	0	0
T50	0	1100	0	0
T51	0	642	0	0
T74	0	1132	0	0
T75	0	642	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	553384	0	304
T1	551	186	0	0
T2	1030	511	0	0
T3	4425	1624	0	2
T4	898	247	0	0
T8	3575	1031	0	2
T13	2806	1027	0	0
T14	1925	1132	0	0
T18	3595	18	0	0
T19	2001	15	0	0
T20	3216	70	0	0
T34	0	0	0	2
T35	0	0	0	2
T45	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	1101	0	75
T3	4425	1	0	0
T4	898	0	0	0
T8	3575	0	0	0
T13	2806	0	0	0
T14	1925	0	0	0
T18	3595	0	0	0
T19	2001	0	0	0
T20	3216	0	0	0
T24	0	4	0	0
T39	0	3	0	1
T40	0	3	0	1
T41	0	58	0	1
T44	0	3	0	1
T45	0	4	0	0
T46	0	0	0	1
T50	2059	0	0	0
T54	1716	0	0	0
T80	0	3	0	1
T81	0	3	0	1
T86	0	3	0	1
T93	0	0	0	1
T94	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	227198914	0	0
T1	551	386	0	0
T2	1030	868	0	0
T3	4425	4374	0	0
T4	898	744	0	0
T8	3575	3506	0	0
T13	2806	2624	0	0
T14	1925	1802	0	0
T18	3595	3517	0	0
T19	2001	1904	0	0
T20	3216	3135	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	152078	0	0
T1	551	272	0	0
T2	1030	592	0	0
T3	4425	0	0	0
T4	898	319	0	0
T8	3575	0	0	0
T13	2806	1084	0	0
T14	1925	1165	0	0
T18	3595	0	0	0
T19	2001	0	0	0
T20	3216	0	0	0
T28	0	33	0	0
T50	0	1100	0	0
T51	0	642	0	0
T74	0	1132	0	0
T75	0	642	0	0