Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	227860550	10404453	0	0
boot_gen_cmd_rd_A	227860550	57168	0	0
boot_ins_cmd_rd_A	227860550	67278	0	0
ctrl_rd_A	227860550	57761	0	0
err_code_test_rd_A	227860550	66489	0	0
intr_enable_rd_A	227860550	65370	0	0
max_num_reqs_between_reseeds_rd_A	227860550	58700	0	0
regwen_rd_A	227860550	67363	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227860550	10404453	0	0
T23	907	0	0	0
T34	533716	291668	0	0
T35	0	54396	0	0
T36	0	176907	0	0
T58	0	35918	0	0
T69	3206	0	0	0
T81	3697	0	0	0
T112	2268	0	0	0
T195	0	376826	0	0
T196	0	193890	0	0
T197	0	577648	0	0
T198	0	36205	0	0
T199	0	74057	0	0
T200	0	89441	0	0
T201	4939	0	0	0
T202	1899	0	0	0
T203	1011	0	0	0
T204	1863	0	0	0
T205	2261	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227860550	57168	0	0
T35	151537	1575	0	0
T36	310623	0	0	0
T58	0	1065	0	0
T114	849	0	0	0
T142	761	0	0	0
T165	793	0	0	0
T172	929	0	0	0
T185	3027	0	0	0
T196	0	2869	0	0
T198	0	1037	0	0
T206	0	6212	0	0
T207	0	4580	0	0
T208	0	4171	0	0
T209	0	4719	0	0
T210	0	3629	0	0
T211	0	3929	0	0
T212	2794	0	0	0
T213	2656	0	0	0
T214	4552	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227860550	67278	0	0
T35	151537	1778	0	0
T36	310623	0	0	0
T58	0	1305	0	0
T114	849	0	0	0
T142	761	0	0	0
T165	793	0	0	0
T172	929	0	0	0
T185	3027	0	0	0
T196	0	3205	0	0
T198	0	1251	0	0
T206	0	7151	0	0
T207	0	5796	0	0
T208	0	4889	0	0
T209	0	5292	0	0
T210	0	4472	0	0
T211	0	4826	0	0
T212	2794	0	0	0
T213	2656	0	0	0
T214	4552	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227860550	57761	0	0
T6	0	1	0	0
T22	1263	9	0	0
T23	0	2	0	0
T24	2486	0	0	0
T25	1770	0	0	0
T26	2346	0	0	0
T35	0	1525	0	0
T39	2039	0	0	0
T40	1625	4	0	0
T45	3207	0	0	0
T51	1341	0	0	0
T53	0	4	0	0
T58	0	945	0	0
T75	1247	0	0	0
T85	8056	0	0	0
T196	0	2868	0	0
T215	0	1	0	0
T216	0	3	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227860550	66489	0	0
T35	151537	1816	0	0
T36	310623	0	0	0
T58	0	1203	0	0
T114	849	0	0	0
T142	761	0	0	0
T165	793	0	0	0
T172	929	0	0	0
T185	3027	0	0	0
T196	0	3426	0	0
T198	0	1218	0	0
T206	0	7212	0	0
T207	0	5451	0	0
T208	0	4948	0	0
T209	0	5202	0	0
T210	0	4028	0	0
T211	0	4593	0	0
T212	2794	0	0	0
T213	2656	0	0	0
T214	4552	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227860550	65370	0	0
T5	2462	0	0	0
T6	1927	0	0	0
T35	0	1696	0	0
T48	11813	26	0	0
T49	12050	0	0	0
T52	1935	0	0	0
T53	2341	0	0	0
T58	0	1246	0	0
T67	3692	0	0	0
T76	5587	0	0	0
T77	1806	0	0	0
T156	6497	0	0	0
T158	0	6	0	0
T196	0	3123	0	0
T198	0	1252	0	0
T206	0	6832	0	0
T207	0	5247	0	0
T217	0	36	0	0
T218	0	160	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227860550	58700	0	0
T35	151537	1341	0	0
T36	310623	0	0	0
T58	0	1050	0	0
T114	849	0	0	0
T142	761	0	0	0
T165	793	0	0	0
T172	929	0	0	0
T185	3027	0	0	0
T196	0	2830	0	0
T198	0	1120	0	0
T206	0	6290	0	0
T207	0	5016	0	0
T208	0	4031	0	0
T209	0	4636	0	0
T210	0	3688	0	0
T211	0	3962	0	0
T212	2794	0	0	0
T213	2656	0	0	0
T214	4552	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227860550	67363	0	0
T35	151537	1856	0	0
T36	310623	0	0	0
T58	0	1192	0	0
T114	849	0	0	0
T142	761	0	0	0
T165	793	0	0	0
T172	929	0	0	0
T185	3027	0	0	0
T196	0	3221	0	0
T198	0	1343	0	0
T206	0	7337	0	0
T207	0	5759	0	0
T208	0	4580	0	0
T209	0	5572	0	0
T210	0	3906	0	0
T211	0	4479	0	0
T212	2794	0	0	0
T213	2656	0	0	0
T214	4552	0	0	0