Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.17	98.24	93.78	97.02	91.86	96.33	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.07	99.92	92.44	82.54	91.86	98.81	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T26,T27,T28

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T14,T16
1	0	Covered	T3,T4,T5

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T4,T9	Yes	T1,T4,T9	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T9,T19	Yes	T1,T9,T19	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T19,T21	Yes	T1,T19,T21	INPUT
edn_i[3].edn_req	Yes	Yes	T1,T18,T38	Yes	T1,T18,T38	INPUT
edn_i[4].edn_req	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	INPUT
edn_i[5].edn_req	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	INPUT
edn_i[6].edn_req	Yes	Yes	T2,T39,T42	Yes	T2,T39,T42	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T4,T9	Yes	T1,T4,T9	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T4,T9	Yes	T1,T4,T9	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T1,T9,T19	Yes	T1,T9,T19	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T1,T9,T19	Yes	T1,T9,T19	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T1,T9,T19	Yes	T1,T9,T19	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T19,T21	Yes	T1,T19,T21	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T43,T44,T45	Yes	T1,T19,T39	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T19,T21	Yes	T1,T19,T21	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T1,T18,T38	Yes	T1,T18,T38	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T1,T38,T44	Yes	T1,T18,T38	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T1,T18,T38	Yes	T1,T18,T38	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T1,T40,T41	Yes	T1,T39,T40	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T1,T46,T47	Yes	T1,T41,T44	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T40,T41,T48	Yes	T40,T41,T49	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T40,T41,T48	Yes	T39,T40,T41	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T2,T42,T41	Yes	T2,T42,T41	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T2,T42,T13	Yes	T2,T39,T42	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T2,T39,T42	Yes	T2,T39,T42	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T9	Yes	T1,T9,T10	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T50,T51,T52	Yes	T50,T51,T52	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T26,T53,T27	Yes	T26,T53,T27	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T26,T53,T27	Yes	T26,T53,T27	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T54,T55	Yes	T4,T54,T55	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	187404959	187225926	0	0
CsrngAppIfOut_A	187404959	187225926	0	0
FpvSecCmCntAlertCheck_A	187404959	128	0	0
FpvSecCmGenCmdFifoRptrCheck_A	187404959	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	187404959	80	0	0
FpvSecCmMainFsmCheck_A	187404959	80	0	0
FpvSecCmRegWeOnehotCheck_A	187404959	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	187404959	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	187404959	80	0	0
IntrEdnCmdReqDoneKnownO_A	187404959	187225926	0	0
TlAReadyKnownO_A	187404959	187225926	0	0
TlDValidKnownO_A	187404959	187225926	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	187404959	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	187404959	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	187404959	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	187404959	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	187404959	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	187404959	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	187404959	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	187404959	557140	0	318
gen_edn_if_asserts[0].EdnDataStable_A	187404959	25914	0	368
gen_edn_if_asserts[0].EdnEndPointOut_A	187404959	187225926	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	187404959	150570	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	187404959	557140	0	318
gen_edn_if_asserts[1].EdnDataStable_A	187404959	5134	0	111
gen_edn_if_asserts[1].EdnEndPointOut_A	187404959	187225926	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	187404959	150570	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	187404959	557140	0	318
gen_edn_if_asserts[2].EdnDataStable_A	187404959	4364	0	100
gen_edn_if_asserts[2].EdnEndPointOut_A	187404959	187225926	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	187404959	150570	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	187404959	557140	0	318
gen_edn_if_asserts[3].EdnDataStable_A	187404959	55523	0	100
gen_edn_if_asserts[3].EdnEndPointOut_A	187404959	187225926	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	187404959	150570	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	187404959	557140	0	318
gen_edn_if_asserts[4].EdnDataStable_A	187404959	3296	0	79
gen_edn_if_asserts[4].EdnEndPointOut_A	187404959	187225926	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	187404959	150570	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	187404959	557140	0	318
gen_edn_if_asserts[5].EdnDataStable_A	187404959	52338	0	84
gen_edn_if_asserts[5].EdnEndPointOut_A	187404959	187225926	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	187404959	150570	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	187404959	557140	0	318
gen_edn_if_asserts[6].EdnDataStable_A	187404959	1619	0	71
gen_edn_if_asserts[6].EdnEndPointOut_A	187404959	187225926	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	187404959	150570	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	128	0	0
T3	46351	20	0	0
T4	1307	0	0	0
T5	1418	0	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	10	0	0
T15	0	1	0	0
T16	0	10	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	2294	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	80	0	0
T3	46351	20	0	0
T4	1307	0	0	0
T5	1418	0	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	10	0	0
T16	0	10	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T63	2294	0	0	0
T64	0	20	0	0
T65	0	20	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	80	0	0
T3	46351	20	0	0
T4	1307	0	0	0
T5	1418	0	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	10	0	0
T16	0	10	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T63	2294	0	0	0
T64	0	20	0	0
T65	0	20	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	80	0	0
T3	46351	20	0	0
T4	1307	0	0	0
T5	1418	0	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	10	0	0
T16	0	10	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T63	2294	0	0	0
T64	0	20	0	0
T65	0	20	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	80	0	0
T3	46351	20	0	0
T4	1307	0	0	0
T5	1418	0	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	10	0	0
T16	0	10	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T63	2294	0	0	0
T64	0	20	0	0
T65	0	20	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	80	0	0
T3	46351	20	0	0
T4	1307	0	0	0
T5	1418	0	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	10	0	0
T16	0	10	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T63	2294	0	0	0
T64	0	20	0	0
T65	0	20	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	80	0	0
T3	46351	20	0	0
T4	1307	0	0	0
T5	1418	0	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	10	0	0
T16	0	10	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T63	2294	0	0	0
T64	0	20	0	0
T65	0	20	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	80	0	0
T3	46351	20	0	0
T4	1307	0	0	0
T5	1418	0	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	10	0	0
T16	0	10	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T63	2294	0	0	0
T64	0	20	0	0
T65	0	20	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	80	0	0
T3	46351	20	0	0
T4	1307	0	0	0
T5	1418	0	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	10	0	0
T16	0	10	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T63	2294	0	0	0
T64	0	20	0	0
T65	0	20	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	80	0	0
T3	46351	20	0	0
T4	1307	0	0	0
T5	1418	0	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	10	0	0
T16	0	10	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T63	2294	0	0	0
T64	0	20	0	0
T65	0	20	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	80	0	0
T3	46351	20	0	0
T4	1307	0	0	0
T5	1418	0	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	10	0	0
T16	0	10	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T63	2294	0	0	0
T64	0	20	0	0
T65	0	20	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	80	0	0
T3	46351	20	0	0
T4	1307	0	0	0
T5	1418	0	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	10	0	0
T16	0	10	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T63	2294	0	0	0
T64	0	20	0	0
T65	0	20	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	80	0	0
T3	46351	20	0	0
T4	1307	0	0	0
T5	1418	0	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	10	0	0
T16	0	10	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T63	2294	0	0	0
T64	0	20	0	0
T65	0	20	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	80	0	0
T3	46351	20	0	0
T4	1307	0	0	0
T5	1418	0	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	10	0	0
T16	0	10	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T63	2294	0	0	0
T64	0	20	0	0
T65	0	20	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	557140	0	318
T1	3553	81	0	0
T2	1533	303	0	0
T3	46351	19597	0	2
T4	1307	550	0	0
T9	5598	183	0	0
T10	2689	305	0	0
T14	0	0	0	2
T17	3002	129	0	0
T18	798	73	0	0
T19	1841	18	0	0
T20	4534	216	0	0
T36	0	0	0	2
T49	0	0	0	2
T53	0	0	0	2
T55	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	25914	0	368
T1	3553	40	0	1
T2	1533	0	0	0
T3	46351	0	0	0
T4	1307	1	0	0
T9	5598	313	0	1
T10	2689	99	0	1
T17	3002	15	0	1
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	675	0	1
T23	0	0	0	1
T26	0	4	0	0
T39	0	26	0	1
T54	0	0	0	1
T63	0	17	0	1
T70	0	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	150570	0	0
T3	46351	18326	0	0
T4	1307	31	0	0
T5	1418	790	0	0
T6	0	1082	0	0
T7	0	1101	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	9071	0	0
T15	0	1173	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T22	0	468	0	0
T63	2294	0	0	0
T71	0	430	0	0
T72	0	362	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	557140	0	318
T1	3553	81	0	0
T2	1533	303	0	0
T3	46351	19597	0	2
T4	1307	550	0	0
T9	5598	183	0	0
T10	2689	305	0	0
T14	0	0	0	2
T17	3002	129	0	0
T18	798	73	0	0
T19	1841	18	0	0
T20	4534	216	0	0
T36	0	0	0	2
T49	0	0	0	2
T53	0	0	0	2
T55	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	5134	0	111
T1	3553	52	0	1
T2	1533	0	0	0
T3	46351	0	0	0
T4	1307	0	0	0
T9	5598	18	0	1
T10	2689	0	0	0
T13	0	57	0	1
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	15	0	1
T20	4534	0	0	0
T39	0	44	0	1
T40	0	3	0	1
T41	0	3	0	1
T44	0	3	0	1
T73	0	842	0	1
T74	0	4	0	0
T75	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	150570	0	0
T3	46351	18326	0	0
T4	1307	31	0	0
T5	1418	790	0	0
T6	0	1082	0	0
T7	0	1101	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	9071	0	0
T15	0	1173	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T22	0	468	0	0
T63	2294	0	0	0
T71	0	430	0	0
T72	0	362	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	557140	0	318
T1	3553	81	0	0
T2	1533	303	0	0
T3	46351	19597	0	2
T4	1307	550	0	0
T9	5598	183	0	0
T10	2689	305	0	0
T14	0	0	0	2
T17	3002	129	0	0
T18	798	73	0	0
T19	1841	18	0	0
T20	4534	216	0	0
T36	0	0	0	2
T49	0	0	0	2
T53	0	0	0	2
T55	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	4364	0	100
T1	3553	3	0	1
T2	1533	0	0	0
T3	46351	0	0	0
T4	1307	0	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	3	0	1
T20	4534	0	0	0
T21	0	3	0	1
T26	0	4	0	1
T39	0	7	0	1
T41	0	3	0	1
T43	0	24	0	1
T44	0	19	0	1
T45	0	4	0	0
T48	0	0	0	1
T73	0	3	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	150570	0	0
T3	46351	18326	0	0
T4	1307	31	0	0
T5	1418	790	0	0
T6	0	1082	0	0
T7	0	1101	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	9071	0	0
T15	0	1173	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T22	0	468	0	0
T63	2294	0	0	0
T71	0	430	0	0
T72	0	362	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	557140	0	318
T1	3553	81	0	0
T2	1533	303	0	0
T3	46351	19597	0	2
T4	1307	550	0	0
T9	5598	183	0	0
T10	2689	305	0	0
T14	0	0	0	2
T17	3002	129	0	0
T18	798	73	0	0
T19	1841	18	0	0
T20	4534	216	0	0
T36	0	0	0	2
T49	0	0	0	2
T53	0	0	0	2
T55	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	55523	0	100
T1	3553	291	0	1
T2	1533	0	0	0
T3	46351	0	0	0
T4	1307	0	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T12	0	64	0	1
T17	3002	0	0	0
T18	798	3	0	1
T19	1841	0	0	0
T20	4534	0	0	0
T27	0	4	0	1
T38	0	3	0	1
T39	0	3	0	1
T41	0	3	0	1
T44	0	16	0	1
T73	0	3	0	1
T76	0	3	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	150570	0	0
T3	46351	18326	0	0
T4	1307	31	0	0
T5	1418	790	0	0
T6	0	1082	0	0
T7	0	1101	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	9071	0	0
T15	0	1173	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T22	0	468	0	0
T63	2294	0	0	0
T71	0	430	0	0
T72	0	362	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	557140	0	318
T1	3553	81	0	0
T2	1533	303	0	0
T3	46351	19597	0	2
T4	1307	550	0	0
T9	5598	183	0	0
T10	2689	305	0	0
T14	0	0	0	2
T17	3002	129	0	0
T18	798	73	0	0
T19	1841	18	0	0
T20	4534	216	0	0
T36	0	0	0	2
T49	0	0	0	2
T53	0	0	0	2
T55	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	3296	0	79
T1	3553	56	0	1
T2	1533	0	0	0
T3	46351	0	0	0
T4	1307	0	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T13	0	3	0	1
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T39	0	3	0	1
T40	0	3	0	1
T41	0	3	0	1
T44	0	3	0	1
T46	0	0	0	1
T48	0	3	0	1
T77	0	3	0	1
T78	0	4	0	0
T79	0	3	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	150570	0	0
T3	46351	18326	0	0
T4	1307	31	0	0
T5	1418	790	0	0
T6	0	1082	0	0
T7	0	1101	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	9071	0	0
T15	0	1173	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T22	0	468	0	0
T63	2294	0	0	0
T71	0	430	0	0
T72	0	362	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	557140	0	318
T1	3553	81	0	0
T2	1533	303	0	0
T3	46351	19597	0	2
T4	1307	550	0	0
T9	5598	183	0	0
T10	2689	305	0	0
T14	0	0	0	2
T17	3002	129	0	0
T18	798	73	0	0
T19	1841	18	0	0
T20	4534	216	0	0
T36	0	0	0	2
T49	0	0	0	2
T53	0	0	0	2
T55	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	52338	0	84
T13	0	3	0	1
T23	1723	0	0	0
T26	2501	0	0	0
T39	1810	3	0	1
T40	2544	36	0	1
T41	0	17	0	1
T42	708	0	0	0
T46	0	63	0	1
T48	0	9	0	1
T49	0	1	0	0
T54	5924	0	0	0
T55	17405	0	0	0
T56	21644	0	0	0
T70	913	0	0	0
T73	5746	0	0	0
T77	0	3	0	1
T79	0	15	0	1
T80	0	3	0	1
T81	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	150570	0	0
T3	46351	18326	0	0
T4	1307	31	0	0
T5	1418	790	0	0
T6	0	1082	0	0
T7	0	1101	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	9071	0	0
T15	0	1173	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T22	0	468	0	0
T63	2294	0	0	0
T71	0	430	0	0
T72	0	362	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	557140	0	318
T1	3553	81	0	0
T2	1533	303	0	0
T3	46351	19597	0	2
T4	1307	550	0	0
T9	5598	183	0	0
T10	2689	305	0	0
T14	0	0	0	2
T17	3002	129	0	0
T18	798	73	0	0
T19	1841	18	0	0
T20	4534	216	0	0
T36	0	0	0	2
T49	0	0	0	2
T53	0	0	0	2
T55	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	1619	0	71
T2	1533	3	0	1
T3	46351	0	0	0
T4	1307	0	0	0
T5	1418	0	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T13	0	15	0	1
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T39	0	3	0	1
T41	0	3	0	1
T42	0	4	0	0
T47	0	0	0	1
T48	0	3	0	1
T77	0	20	0	1
T79	0	41	0	1
T81	0	57	0	1
T82	0	4	0	0
T83	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	150570	0	0
T3	46351	18326	0	0
T4	1307	31	0	0
T5	1418	790	0	0
T6	0	1082	0	0
T7	0	1101	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	9071	0	0
T15	0	1173	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T22	0	468	0	0
T63	2294	0	0	0
T71	0	430	0	0
T72	0	362	0	0