Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	187933064	7872037	0	0
boot_gen_cmd_rd_A	187933064	51072	0	0
boot_ins_cmd_rd_A	187933064	58302	0	0
ctrl_rd_A	187933064	50114	0	0
err_code_test_rd_A	187933064	57044	0	0
intr_enable_rd_A	187933064	58834	0	0
max_num_reqs_between_reseeds_rd_A	187933064	53278	0	0
regwen_rd_A	187933064	58527	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187933064	7872037	0	0
T11	1501	0	0	0
T12	3159	0	0	0
T27	2775	0	0	0
T35	273033	112463	0	0
T36	0	196855	0	0
T37	0	286614	0	0
T43	2073	0	0	0
T44	1428	0	0	0
T53	1197	0	0	0
T66	1207	0	0	0
T71	897	0	0	0
T92	0	103071	0	0
T98	0	92429	0	0
T204	0	260650	0	0
T205	0	97319	0	0
T206	0	275464	0	0
T207	0	166824	0	0
T208	0	106625	0	0
T209	2542	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187933064	51072	0	0
T7	2306	0	0	0
T15	2031	0	0	0
T36	583359	6073	0	0
T48	3030	0	0	0
T68	29512	0	0	0
T69	3545	0	0	0
T76	1167	0	0	0
T92	0	3087	0	0
T206	0	8195	0	0
T210	0	4686	0	0
T211	0	1187	0	0
T212	0	11547	0	0
T213	0	2659	0	0
T214	0	2568	0	0
T215	0	2706	0	0
T216	0	5039	0	0
T217	2207	0	0	0
T218	2615	0	0	0
T219	1604	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187933064	58302	0	0
T7	2306	0	0	0
T15	2031	0	0	0
T36	583359	6647	0	0
T48	3030	0	0	0
T68	29512	0	0	0
T69	3545	0	0	0
T76	1167	0	0	0
T92	0	3670	0	0
T206	0	9341	0	0
T210	0	5633	0	0
T211	0	1240	0	0
T212	0	13261	0	0
T213	0	3093	0	0
T214	0	2968	0	0
T215	0	2974	0	0
T216	0	5686	0	0
T217	2207	0	0	0
T218	2615	0	0	0
T219	1604	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187933064	50114	0	0
T7	2306	0	0	0
T15	2031	0	0	0
T36	583359	5810	0	0
T48	3030	0	0	0
T68	29512	0	0	0
T69	3545	0	0	0
T76	1167	0	0	0
T92	0	2824	0	0
T95	0	1	0	0
T96	0	8	0	0
T135	0	7	0	0
T159	0	2	0	0
T206	0	8084	0	0
T210	0	5017	0	0
T217	2207	0	0	0
T218	2615	0	0	0
T219	1604	0	0	0
T220	0	5	0	0
T221	0	3	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187933064	57044	0	0
T7	2306	0	0	0
T15	2031	0	0	0
T36	583359	6316	0	0
T48	3030	0	0	0
T68	29512	0	0	0
T69	3545	0	0	0
T76	1167	0	0	0
T92	0	3410	0	0
T206	0	9539	0	0
T210	0	5542	0	0
T211	0	1102	0	0
T212	0	13077	0	0
T213	0	2919	0	0
T214	0	2746	0	0
T215	0	2891	0	0
T216	0	5988	0	0
T217	2207	0	0	0
T218	2615	0	0	0
T219	1604	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187933064	58834	0	0
T7	2306	0	0	0
T15	2031	0	0	0
T36	583359	6268	0	0
T48	3030	0	0	0
T68	29512	56	0	0
T69	3545	0	0	0
T76	1167	0	0	0
T92	0	3358	0	0
T95	0	80	0	0
T96	0	2	0	0
T206	0	8837	0	0
T210	0	5243	0	0
T217	2207	0	0	0
T218	2615	0	0	0
T219	1604	0	0	0
T221	0	106	0	0
T222	0	55	0	0
T223	0	39	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187933064	53278	0	0
T7	2306	0	0	0
T15	2031	0	0	0
T36	583359	6022	0	0
T48	3030	0	0	0
T68	29512	0	0	0
T69	3545	0	0	0
T76	1167	0	0	0
T92	0	3039	0	0
T206	0	8119	0	0
T210	0	5196	0	0
T211	0	1050	0	0
T212	0	11988	0	0
T213	0	2825	0	0
T214	0	2460	0	0
T215	0	2573	0	0
T216	0	5066	0	0
T217	2207	0	0	0
T218	2615	0	0	0
T219	1604	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187933064	58527	0	0
T7	2306	0	0	0
T15	2031	0	0	0
T36	583359	6831	0	0
T48	3030	0	0	0
T68	29512	0	0	0
T69	3545	0	0	0
T76	1167	0	0	0
T92	0	3319	0	0
T206	0	9194	0	0
T210	0	5354	0	0
T211	0	1119	0	0
T212	0	13382	0	0
T213	0	3054	0	0
T214	0	2962	0	0
T215	0	2932	0	0
T216	0	5339	0	0
T217	2207	0	0	0
T218	2615	0	0	0
T219	1604	0	0	0