Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.20	98.25	93.91	97.07	91.86	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.16	99.92	92.66	82.84	91.86	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T10

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T19,T20
1	0	Covered	T4,T6,T7

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T24,T34,T35	Yes	T24,T34,T35	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T11,T29,T15	Yes	T11,T29,T15	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T36,T37	Yes	T1,T36,T37	INPUT
edn_i[3].edn_req	Yes	Yes	T38,T36,T37	Yes	T38,T36,T37	INPUT
edn_i[4].edn_req	Yes	Yes	T37,T12,T39	Yes	T37,T12,T39	INPUT
edn_i[5].edn_req	Yes	Yes	T8,T40,T41	Yes	T8,T40,T41	INPUT
edn_i[6].edn_req	Yes	Yes	T4,T38,T12	Yes	T4,T38,T12	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T11,T29,T15	Yes	T11,T29,T15	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T11,T29,T42	Yes	T11,T29,T42	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T11,T29,T15	Yes	T11,T29,T15	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T36,T37	Yes	T1,T36,T37	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T43,T44,T45	Yes	T36,T37,T43	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T36,T37	Yes	T1,T36,T37	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T38,T37,T46	Yes	T38,T36,T37	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T38,T37,T46	Yes	T38,T37,T46	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T38,T36,T37	Yes	T38,T36,T37	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T37,T12,T43	Yes	T37,T12,T40	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T37,T47,T48	Yes	T37,T39,T44	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T37,T12,T39	Yes	T37,T12,T39	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T40,T41,T47	Yes	T40,T41,T23	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T40,T41,T49	Yes	T40,T41,T23	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T40,T41,T23	Yes	T40,T41,T23	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T38,T50,T41	Yes	T38,T12,T50	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T50,T51,T45	Yes	T12,T50,T51	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T38,T12,T50	Yes	T38,T12,T50	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T3	Yes	T3,T5,T24	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T3,T5,T24	Yes	T3,T5,T24	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T2,T25,T52	Yes	T2,T25,T52	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T10	Yes	T1,T2,T10	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T6,T53	Yes	T4,T6,T53	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T10	Yes	T1,T2,T10	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T6,T53	Yes	T4,T6,T53	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T5,T24,T34	Yes	T5,T24,T34	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T5,T6,T24	Yes	T5,T6,T24	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	220552487	220371228	0	0
CsrngAppIfOut_A	220552487	220371228	0	0
FpvSecCmCntAlertCheck_A	220552487	123	0	0
FpvSecCmGenCmdFifoRptrCheck_A	220552487	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	220552487	70	0	0
FpvSecCmMainFsmCheck_A	220552487	70	0	0
FpvSecCmRegWeOnehotCheck_A	220552487	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	220552487	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	220552487	70	0	0
IntrEdnCmdReqDoneKnownO_A	220552487	220371228	0	0
TlAReadyKnownO_A	220552487	220371228	0	0
TlDValidKnownO_A	220552487	220371228	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	220552487	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	220552487	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	220552487	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	220552487	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	220552487	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	220552487	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	220552487	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	220552487	614377	0	308
gen_edn_if_asserts[0].EdnDataStable_A	220552487	70643	0	439
gen_edn_if_asserts[0].EdnEndPointOut_A	220552487	220371228	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	220552487	148052	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	220552487	614377	0	308
gen_edn_if_asserts[1].EdnDataStable_A	220552487	5762	0	134
gen_edn_if_asserts[1].EdnEndPointOut_A	220552487	220371228	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	220552487	148052	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	220552487	614377	0	308
gen_edn_if_asserts[2].EdnDataStable_A	220552487	4527	0	128
gen_edn_if_asserts[2].EdnEndPointOut_A	220552487	220371228	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	220552487	148052	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	220552487	614377	0	308
gen_edn_if_asserts[3].EdnDataStable_A	220552487	6142	0	113
gen_edn_if_asserts[3].EdnEndPointOut_A	220552487	220371228	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	220552487	148052	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	220552487	614377	0	308
gen_edn_if_asserts[4].EdnDataStable_A	220552487	3566	0	107
gen_edn_if_asserts[4].EdnEndPointOut_A	220552487	220371228	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	220552487	148052	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	220552487	614377	0	308
gen_edn_if_asserts[5].EdnDataStable_A	220552487	4518	0	94
gen_edn_if_asserts[5].EdnEndPointOut_A	220552487	220371228	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	220552487	148052	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	220552487	614377	0	308
gen_edn_if_asserts[6].EdnDataStable_A	220552487	3086	0	87
gen_edn_if_asserts[6].EdnEndPointOut_A	220552487	220371228	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	220552487	148052	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	220371228	0	0
T1	2202	2110	0	0
T2	2940	2862	0	0
T3	4388	4324	0	0
T4	508	395	0	0
T5	26607	25887	0	0
T6	2027	1888	0	0
T10	2590	2493	0	0
T11	3730	3674	0	0
T24	338039	338030	0	0
T25	2084	2002	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	220371228	0	0
T1	2202	2110	0	0
T2	2940	2862	0	0
T3	4388	4324	0	0
T4	508	395	0	0
T5	26607	25887	0	0
T6	2027	1888	0	0
T10	2590	2493	0	0
T11	3730	3674	0	0
T24	338039	338030	0	0
T25	2084	2002	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	123	0	0
T16	1938	1	0	0
T17	0	10	0	0
T18	0	1	0	0
T19	0	20	0	0
T20	0	10	0	0
T22	4410	0	0	0
T23	6673	0	0	0
T43	3257	0	0	0
T51	2558	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	1010	0	0	0
T60	1912	0	0	0
T61	1307	0	0	0
T62	634700	0	0	0
T63	2009	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	70	0	0
T17	21755	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T64	0	10	0	0
T65	0	20	0	0
T66	1848	0	0	0
T67	6659	0	0	0
T68	2038	0	0	0
T69	2665	0	0	0
T70	5764	0	0	0
T71	1736	0	0	0
T72	1280	0	0	0
T73	723	0	0	0
T74	364633	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	70	0	0
T17	21755	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T64	0	10	0	0
T65	0	20	0	0
T66	1848	0	0	0
T67	6659	0	0	0
T68	2038	0	0	0
T69	2665	0	0	0
T70	5764	0	0	0
T71	1736	0	0	0
T72	1280	0	0	0
T73	723	0	0	0
T74	364633	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	70	0	0
T17	21755	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T64	0	10	0	0
T65	0	20	0	0
T66	1848	0	0	0
T67	6659	0	0	0
T68	2038	0	0	0
T69	2665	0	0	0
T70	5764	0	0	0
T71	1736	0	0	0
T72	1280	0	0	0
T73	723	0	0	0
T74	364633	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	70	0	0
T17	21755	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T64	0	10	0	0
T65	0	20	0	0
T66	1848	0	0	0
T67	6659	0	0	0
T68	2038	0	0	0
T69	2665	0	0	0
T70	5764	0	0	0
T71	1736	0	0	0
T72	1280	0	0	0
T73	723	0	0	0
T74	364633	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	70	0	0
T17	21755	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T64	0	10	0	0
T65	0	20	0	0
T66	1848	0	0	0
T67	6659	0	0	0
T68	2038	0	0	0
T69	2665	0	0	0
T70	5764	0	0	0
T71	1736	0	0	0
T72	1280	0	0	0
T73	723	0	0	0
T74	364633	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	70	0	0
T17	21755	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T64	0	10	0	0
T65	0	20	0	0
T66	1848	0	0	0
T67	6659	0	0	0
T68	2038	0	0	0
T69	2665	0	0	0
T70	5764	0	0	0
T71	1736	0	0	0
T72	1280	0	0	0
T73	723	0	0	0
T74	364633	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	220371228	0	0
T1	2202	2110	0	0
T2	2940	2862	0	0
T3	4388	4324	0	0
T4	508	395	0	0
T5	26607	25887	0	0
T6	2027	1888	0	0
T10	2590	2493	0	0
T11	3730	3674	0	0
T24	338039	338030	0	0
T25	2084	2002	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	220371228	0	0
T1	2202	2110	0	0
T2	2940	2862	0	0
T3	4388	4324	0	0
T4	508	395	0	0
T5	26607	25887	0	0
T6	2027	1888	0	0
T10	2590	2493	0	0
T11	3730	3674	0	0
T24	338039	338030	0	0
T25	2084	2002	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	220371228	0	0
T1	2202	2110	0	0
T2	2940	2862	0	0
T3	4388	4324	0	0
T4	508	395	0	0
T5	26607	25887	0	0
T6	2027	1888	0	0
T10	2590	2493	0	0
T11	3730	3674	0	0
T24	338039	338030	0	0
T25	2084	2002	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	70	0	0
T17	21755	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T64	0	10	0	0
T65	0	20	0	0
T66	1848	0	0	0
T67	6659	0	0	0
T68	2038	0	0	0
T69	2665	0	0	0
T70	5764	0	0	0
T71	1736	0	0	0
T72	1280	0	0	0
T73	723	0	0	0
T74	364633	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	70	0	0
T17	21755	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T64	0	10	0	0
T65	0	20	0	0
T66	1848	0	0	0
T67	6659	0	0	0
T68	2038	0	0	0
T69	2665	0	0	0
T70	5764	0	0	0
T71	1736	0	0	0
T72	1280	0	0	0
T73	723	0	0	0
T74	364633	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	70	0	0
T17	21755	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T64	0	10	0	0
T65	0	20	0	0
T66	1848	0	0	0
T67	6659	0	0	0
T68	2038	0	0	0
T69	2665	0	0	0
T70	5764	0	0	0
T71	1736	0	0	0
T72	1280	0	0	0
T73	723	0	0	0
T74	364633	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	70	0	0
T17	21755	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T64	0	10	0	0
T65	0	20	0	0
T66	1848	0	0	0
T67	6659	0	0	0
T68	2038	0	0	0
T69	2665	0	0	0
T70	5764	0	0	0
T71	1736	0	0	0
T72	1280	0	0	0
T73	723	0	0	0
T74	364633	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	70	0	0
T17	21755	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T64	0	10	0	0
T65	0	20	0	0
T66	1848	0	0	0
T67	6659	0	0	0
T68	2038	0	0	0
T69	2665	0	0	0
T70	5764	0	0	0
T71	1736	0	0	0
T72	1280	0	0	0
T73	723	0	0	0
T74	364633	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	70	0	0
T17	21755	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T64	0	10	0	0
T65	0	20	0	0
T66	1848	0	0	0
T67	6659	0	0	0
T68	2038	0	0	0
T69	2665	0	0	0
T70	5764	0	0	0
T71	1736	0	0	0
T72	1280	0	0	0
T73	723	0	0	0
T74	364633	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	70	0	0
T17	21755	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T64	0	10	0	0
T65	0	20	0	0
T66	1848	0	0	0
T67	6659	0	0	0
T68	2038	0	0	0
T69	2665	0	0	0
T70	5764	0	0	0
T71	1736	0	0	0
T72	1280	0	0	0
T73	723	0	0	0
T74	364633	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	614377	0	308
T1	2202	295	0	0
T2	2940	468	0	0
T3	4388	25	0	0
T4	508	182	0	0
T5	26607	1677	0	0
T6	2027	1051	0	0
T10	2590	459	0	0
T11	3730	76	0	0
T15	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T24	338039	255	0	0
T25	2084	182	0	0
T34	0	0	0	2
T35	0	0	0	2
T53	0	0	0	2
T62	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	70643	0	439
T1	2202	4	0	1
T2	2940	8	0	1
T3	4388	37	0	1
T4	508	0	0	0
T5	26607	24	0	1
T6	2027	1	0	0
T10	2590	4	0	1
T11	3730	0	0	0
T24	338039	48	0	1
T25	2084	8	0	1
T34	0	68	0	0
T37	0	54	0	1
T78	0	0	0	1
T79	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	220371228	0	0
T1	2202	2110	0	0
T2	2940	2862	0	0
T3	4388	4324	0	0
T4	508	395	0	0
T5	26607	25887	0	0
T6	2027	1888	0	0
T10	2590	2493	0	0
T11	3730	3674	0	0
T24	338039	338030	0	0
T25	2084	2002	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	148052	0	0
T4	508	245	0	0
T5	26607	0	0	0
T6	2027	7	0	0
T7	0	1139	0	0
T8	0	384	0	0
T9	0	637	0	0
T10	2590	0	0	0
T11	3730	0	0	0
T24	338039	0	0	0
T25	2084	0	0	0
T29	0	23	0	0
T30	0	7	0	0
T34	316295	0	0	0
T36	1665	0	0	0
T38	1483	0	0	0
T80	0	549	0	0
T81	0	651	0	0
T82	0	412	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	614377	0	308
T1	2202	295	0	0
T2	2940	468	0	0
T3	4388	25	0	0
T4	508	182	0	0
T5	26607	1677	0	0
T6	2027	1051	0	0
T10	2590	459	0	0
T11	3730	76	0	0
T15	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T24	338039	255	0	0
T25	2084	182	0	0
T34	0	0	0	2
T35	0	0	0	2
T53	0	0	0	2
T62	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	5762	0	134
T7	2416	0	0	0
T11	3730	15	0	1
T15	0	4	0	0
T22	0	4	0	0
T29	2062	1	0	0
T34	316295	0	0	0
T36	1665	0	0	0
T37	2382	0	0	0
T38	1483	0	0	0
T40	0	56	0	1
T42	0	15	0	1
T44	0	3	0	1
T47	0	0	0	1
T48	0	0	0	1
T53	966	0	0	0
T78	1890	0	0	0
T79	1391	0	0	0
T83	0	3	0	1
T84	0	14	0	1
T85	0	1	0	0
T86	0	0	0	1
T87	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	220371228	0	0
T1	2202	2110	0	0
T2	2940	2862	0	0
T3	4388	4324	0	0
T4	508	395	0	0
T5	26607	25887	0	0
T6	2027	1888	0	0
T10	2590	2493	0	0
T11	3730	3674	0	0
T24	338039	338030	0	0
T25	2084	2002	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	148052	0	0
T4	508	245	0	0
T5	26607	0	0	0
T6	2027	7	0	0
T7	0	1139	0	0
T8	0	384	0	0
T9	0	637	0	0
T10	2590	0	0	0
T11	3730	0	0	0
T24	338039	0	0	0
T25	2084	0	0	0
T29	0	23	0	0
T30	0	7	0	0
T34	316295	0	0	0
T36	1665	0	0	0
T38	1483	0	0	0
T80	0	549	0	0
T81	0	651	0	0
T82	0	412	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	614377	0	308
T1	2202	295	0	0
T2	2940	468	0	0
T3	4388	25	0	0
T4	508	182	0	0
T5	26607	1677	0	0
T6	2027	1051	0	0
T10	2590	459	0	0
T11	3730	76	0	0
T15	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T24	338039	255	0	0
T25	2084	182	0	0
T34	0	0	0	2
T35	0	0	0	2
T53	0	0	0	2
T62	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	4527	0	128
T1	2202	4	0	0
T2	2940	0	0	0
T3	4388	0	0	0
T4	508	0	0	0
T5	26607	0	0	0
T6	2027	0	0	0
T10	2590	0	0	0
T11	3730	0	0	0
T12	0	3	0	1
T24	338039	0	0	0
T25	2084	0	0	0
T36	0	7	0	1
T37	0	3	0	1
T40	0	3	0	1
T43	0	73	0	1
T44	0	48	0	1
T45	0	0	0	1
T47	0	0	0	1
T51	0	4	0	1
T87	0	0	0	1
T88	0	1	0	0
T89	0	4	0	0

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	220371228	0	0
T1	2202	2110	0	0
T2	2940	2862	0	0
T3	4388	4324	0	0
T4	508	395	0	0
T5	26607	25887	0	0
T6	2027	1888	0	0
T10	2590	2493	0	0
T11	3730	3674	0	0
T24	338039	338030	0	0
T25	2084	2002	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	148052	0	0
T4	508	245	0	0
T5	26607	0	0	0
T6	2027	7	0	0
T7	0	1139	0	0
T8	0	384	0	0
T9	0	637	0	0
T10	2590	0	0	0
T11	3730	0	0	0
T24	338039	0	0	0
T25	2084	0	0	0
T29	0	23	0	0
T30	0	7	0	0
T34	316295	0	0	0
T36	1665	0	0	0
T38	1483	0	0	0
T80	0	549	0	0
T81	0	651	0	0
T82	0	412	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	614377	0	308
T1	2202	295	0	0
T2	2940	468	0	0
T3	4388	25	0	0
T4	508	182	0	0
T5	26607	1677	0	0
T6	2027	1051	0	0
T10	2590	459	0	0
T11	3730	76	0	0
T15	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T24	338039	255	0	0
T25	2084	182	0	0
T34	0	0	0	2
T35	0	0	0	2
T53	0	0	0	2
T62	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	6142	0	113
T7	2416	0	0	0
T12	0	15	0	1
T21	0	4	0	0
T29	2062	0	0	0
T34	316295	0	0	0
T36	1665	3	0	1
T37	2382	22	0	1
T38	1483	21	0	1
T40	0	6	0	1
T41	0	0	0	1
T46	0	56	0	1
T53	966	0	0	0
T78	1890	0	0	0
T79	1391	0	0	0
T90	0	4	0	1
T91	0	3	0	1
T92	0	3	0	1
T93	3951	0	0	0

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	220371228	0	0
T1	2202	2110	0	0
T2	2940	2862	0	0
T3	4388	4324	0	0
T4	508	395	0	0
T5	26607	25887	0	0
T6	2027	1888	0	0
T10	2590	2493	0	0
T11	3730	3674	0	0
T24	338039	338030	0	0
T25	2084	2002	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	148052	0	0
T4	508	245	0	0
T5	26607	0	0	0
T6	2027	7	0	0
T7	0	1139	0	0
T8	0	384	0	0
T9	0	637	0	0
T10	2590	0	0	0
T11	3730	0	0	0
T24	338039	0	0	0
T25	2084	0	0	0
T29	0	23	0	0
T30	0	7	0	0
T34	316295	0	0	0
T36	1665	0	0	0
T38	1483	0	0	0
T80	0	549	0	0
T81	0	651	0	0
T82	0	412	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	614377	0	308
T1	2202	295	0	0
T2	2940	468	0	0
T3	4388	25	0	0
T4	508	182	0	0
T5	26607	1677	0	0
T6	2027	1051	0	0
T10	2590	459	0	0
T11	3730	76	0	0
T15	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T24	338039	255	0	0
T25	2084	182	0	0
T34	0	0	0	2
T35	0	0	0	2
T53	0	0	0	2
T62	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	3566	0	107
T12	0	3	0	1
T15	2547	0	0	0
T26	977	0	0	0
T29	2062	0	0	0
T37	2382	17	0	1
T39	0	4	0	1
T40	0	3	0	1
T43	0	3	0	1
T44	0	3	0	1
T46	3171	0	0	0
T47	0	35	0	1
T48	0	69	0	1
T75	1834	0	0	0
T78	1890	0	0	0
T79	1391	0	0	0
T87	0	28	0	1
T93	3951	0	0	0
T94	0	4	0	1
T95	1950	0	0	0

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	220371228	0	0
T1	2202	2110	0	0
T2	2940	2862	0	0
T3	4388	4324	0	0
T4	508	395	0	0
T5	26607	25887	0	0
T6	2027	1888	0	0
T10	2590	2493	0	0
T11	3730	3674	0	0
T24	338039	338030	0	0
T25	2084	2002	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	148052	0	0
T4	508	245	0	0
T5	26607	0	0	0
T6	2027	7	0	0
T7	0	1139	0	0
T8	0	384	0	0
T9	0	637	0	0
T10	2590	0	0	0
T11	3730	0	0	0
T24	338039	0	0	0
T25	2084	0	0	0
T29	0	23	0	0
T30	0	7	0	0
T34	316295	0	0	0
T36	1665	0	0	0
T38	1483	0	0	0
T80	0	549	0	0
T81	0	651	0	0
T82	0	412	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	614377	0	308
T1	2202	295	0	0
T2	2940	468	0	0
T3	4388	25	0	0
T4	508	182	0	0
T5	26607	1677	0	0
T6	2027	1051	0	0
T10	2590	459	0	0
T11	3730	76	0	0
T15	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T24	338039	255	0	0
T25	2084	182	0	0
T34	0	0	0	2
T35	0	0	0	2
T53	0	0	0	2
T62	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	4518	0	94
T16	1938	0	0	0
T22	4410	0	0	0
T23	6673	3	0	1
T40	2219	16	0	1
T41	2061	39	0	1
T47	0	6	0	1
T48	0	10	0	1
T49	0	11	0	1
T59	1010	0	0	0
T60	1912	0	0	0
T76	249608	0	0	0
T88	1239	0	0	0
T96	0	3	0	1
T97	0	3	0	1
T98	0	33	0	1
T99	0	3	0	1
T100	784	0	0	0

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	220371228	0	0
T1	2202	2110	0	0
T2	2940	2862	0	0
T3	4388	4324	0	0
T4	508	395	0	0
T5	26607	25887	0	0
T6	2027	1888	0	0
T10	2590	2493	0	0
T11	3730	3674	0	0
T24	338039	338030	0	0
T25	2084	2002	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	148052	0	0
T4	508	245	0	0
T5	26607	0	0	0
T6	2027	7	0	0
T7	0	1139	0	0
T8	0	384	0	0
T9	0	637	0	0
T10	2590	0	0	0
T11	3730	0	0	0
T24	338039	0	0	0
T25	2084	0	0	0
T29	0	23	0	0
T30	0	7	0	0
T34	316295	0	0	0
T36	1665	0	0	0
T38	1483	0	0	0
T80	0	549	0	0
T81	0	651	0	0
T82	0	412	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	614377	0	308
T1	2202	295	0	0
T2	2940	468	0	0
T3	4388	25	0	0
T4	508	182	0	0
T5	26607	1677	0	0
T6	2027	1051	0	0
T10	2590	459	0	0
T11	3730	76	0	0
T15	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T24	338039	255	0	0
T25	2084	182	0	0
T34	0	0	0	2
T35	0	0	0	2
T53	0	0	0	2
T62	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	3086	0	87
T7	2416	0	0	0
T12	0	3	0	1
T29	2062	0	0	0
T34	316295	0	0	0
T36	1665	0	0	0
T37	2382	0	0	0
T38	1483	3	0	1
T41	0	3	0	1
T44	0	3	0	1
T45	0	15	0	1
T50	0	4	0	0
T51	0	4	0	0
T53	966	0	0	0
T78	1890	0	0	0
T79	1391	0	0	0
T87	0	3	0	1
T93	3951	0	0	0
T98	0	0	0	1
T101	0	3	0	1
T102	0	4	0	0
T103	0	0	0	1
T104	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	220371228	0	0
T1	2202	2110	0	0
T2	2940	2862	0	0
T3	4388	4324	0	0
T4	508	395	0	0
T5	26607	25887	0	0
T6	2027	1888	0	0
T10	2590	2493	0	0
T11	3730	3674	0	0
T24	338039	338030	0	0
T25	2084	2002	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220552487	148052	0	0
T4	508	245	0	0
T5	26607	0	0	0
T6	2027	7	0	0
T7	0	1139	0	0
T8	0	384	0	0
T9	0	637	0	0
T10	2590	0	0	0
T11	3730	0	0	0
T24	338039	0	0	0
T25	2084	0	0	0
T29	0	23	0	0
T30	0	7	0	0
T34	316295	0	0	0
T36	1665	0	0	0
T38	1483	0	0	0
T80	0	549	0	0
T81	0	651	0	0
T82	0	412	0	0