Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	221082572	9501658	0	0
boot_gen_cmd_rd_A	221082572	85649	0	0
boot_ins_cmd_rd_A	221082572	96121	0	0
ctrl_rd_A	221082572	85710	0	0
err_code_test_rd_A	221082572	95663	0	0
intr_enable_rd_A	221082572	96250	0	0
max_num_reqs_between_reseeds_rd_A	221082572	85873	0	0
regwen_rd_A	221082572	99063	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221082572	9501658	0	0
T7	2416	0	0	0
T11	3730	0	0	0
T24	338039	197578	0	0
T25	2084	0	0	0
T34	316295	176174	0	0
T35	0	141413	0	0
T36	1665	0	0	0
T37	2382	0	0	0
T38	1483	0	0	0
T53	966	0	0	0
T62	0	351894	0	0
T74	0	209719	0	0
T76	0	102554	0	0
T78	1890	0	0	0
T116	0	40511	0	0
T117	0	219397	0	0
T237	0	114195	0	0
T238	0	51641	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221082572	85649	0	0
T87	4147	0	0	0
T94	1800	0	0	0
T96	3770	0	0	0
T102	2934	0	0	0
T117	611354	3238	0	0
T120	2001	0	0	0
T158	1857	0	0	0
T172	2108	0	0	0
T224	1899	0	0	0
T238	0	1407	0	0
T239	0	1712	0	0
T240	0	1233	0	0
T241	0	2337	0	0
T242	0	5330	0	0
T243	0	1217	0	0
T244	0	7632	0	0
T245	0	7438	0	0
T246	0	1418	0	0
T247	5088	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221082572	96121	0	0
T87	4147	0	0	0
T94	1800	0	0	0
T96	3770	0	0	0
T102	2934	0	0	0
T117	611354	3648	0	0
T120	2001	0	0	0
T158	1857	0	0	0
T172	2108	0	0	0
T224	1899	0	0	0
T238	0	1597	0	0
T239	0	1644	0	0
T240	0	1335	0	0
T241	0	2890	0	0
T242	0	5852	0	0
T243	0	1303	0	0
T244	0	8700	0	0
T245	0	8079	0	0
T246	0	1622	0	0
T247	5088	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221082572	85710	0	0
T87	4147	0	0	0
T94	1800	0	0	0
T96	3770	0	0	0
T102	2934	0	0	0
T117	611354	3188	0	0
T120	2001	0	0	0
T158	1857	0	0	0
T172	2108	0	0	0
T224	1899	0	0	0
T238	0	1470	0	0
T239	0	1679	0	0
T240	0	1236	0	0
T241	0	2398	0	0
T242	0	5303	0	0
T247	5088	8	0	0
T248	0	5	0	0
T249	0	6	0	0
T250	0	2	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221082572	95663	0	0
T87	4147	0	0	0
T94	1800	0	0	0
T96	3770	0	0	0
T102	2934	0	0	0
T117	611354	3518	0	0
T120	2001	0	0	0
T158	1857	0	0	0
T172	2108	0	0	0
T224	1899	0	0	0
T238	0	1764	0	0
T239	0	1659	0	0
T240	0	1338	0	0
T241	0	2564	0	0
T242	0	5707	0	0
T243	0	1264	0	0
T244	0	8935	0	0
T245	0	8129	0	0
T246	0	1876	0	0
T247	5088	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221082572	96250	0	0
T12	2456	0	0	0
T35	354613	0	0	0
T39	1734	0	0	0
T52	2627	0	0	0
T80	1038	0	0	0
T81	2158	0	0	0
T83	2939	0	0	0
T91	1124	0	0	0
T114	4338	22	0	0
T117	0	3626	0	0
T118	1077	0	0	0
T238	0	1576	0	0
T239	0	1795	0	0
T240	0	1554	0	0
T241	0	2771	0	0
T242	0	4845	0	0
T249	0	112	0	0
T251	0	48	0	0
T252	0	111	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221082572	85873	0	0
T87	4147	0	0	0
T94	1800	0	0	0
T96	3770	0	0	0
T102	2934	0	0	0
T117	611354	3246	0	0
T120	2001	0	0	0
T158	1857	0	0	0
T172	2108	0	0	0
T224	1899	0	0	0
T238	0	1597	0	0
T239	0	1643	0	0
T240	0	1317	0	0
T241	0	2405	0	0
T242	0	4861	0	0
T243	0	1100	0	0
T244	0	7649	0	0
T245	0	6947	0	0
T246	0	1605	0	0
T247	5088	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221082572	99063	0	0
T87	4147	0	0	0
T94	1800	0	0	0
T96	3770	0	0	0
T102	2934	0	0	0
T117	611354	3776	0	0
T120	2001	0	0	0
T158	1857	0	0	0
T172	2108	0	0	0
T224	1899	0	0	0
T238	0	1856	0	0
T239	0	1885	0	0
T240	0	1282	0	0
T241	0	2913	0	0
T242	0	5975	0	0
T243	0	1257	0	0
T244	0	8719	0	0
T245	0	8457	0	0
T246	0	1713	0	0
T247	5088	0	0	0