Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	217389195	9905384	0	0
boot_gen_cmd_rd_A	217389195	49650	0	0
boot_ins_cmd_rd_A	217389195	55855	0	0
ctrl_rd_A	217389195	50271	0	0
err_code_test_rd_A	217389195	57518	0	0
intr_enable_rd_A	217389195	58934	0	0
max_num_reqs_between_reseeds_rd_A	217389195	51526	0	0
regwen_rd_A	217389195	60002	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217389195	9905384	0	0
T4	450859	254411	0	0
T5	1368	0	0	0
T6	821	0	0	0
T10	6664	0	0	0
T11	2668	0	0	0
T15	491	0	0	0
T28	854	0	0	0
T32	2363	0	0	0
T40	0	278009	0	0
T41	0	107465	0	0
T42	2814	0	0	0
T49	984	0	0	0
T103	0	237761	0	0
T104	0	516410	0	0
T105	0	63279	0	0
T231	0	202156	0	0
T232	0	169391	0	0
T233	0	96716	0	0
T234	0	68744	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217389195	49650	0	0
T132	2596	0	0	0
T146	1839	0	0	0
T228	1616	0	0	0
T235	167214	1707	0	0
T236	0	3057	0	0
T237	0	4131	0	0
T238	0	509	0	0
T239	0	8791	0	0
T240	0	5321	0	0
T241	0	3139	0	0
T242	0	3006	0	0
T243	0	2775	0	0
T244	0	3450	0	0
T245	7625	0	0	0
T246	2230	0	0	0
T247	2914	0	0	0
T248	5244	0	0	0
T249	1483	0	0	0
T250	5672	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217389195	55855	0	0
T132	2596	0	0	0
T146	1839	0	0	0
T228	1616	0	0	0
T235	167214	1881	0	0
T236	0	3275	0	0
T237	0	4205	0	0
T238	0	657	0	0
T239	0	9695	0	0
T240	0	6071	0	0
T241	0	3687	0	0
T242	0	3734	0	0
T243	0	3185	0	0
T244	0	3998	0	0
T245	7625	0	0	0
T246	2230	0	0	0
T247	2914	0	0	0
T248	5244	0	0	0
T249	1483	0	0	0
T250	5672	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217389195	50271	0	0
T4	450859	0	0	0
T5	1368	0	0	0
T6	821	0	0	0
T10	6664	0	0	0
T15	491	0	0	0
T19	2559	2	0	0
T23	2711	0	0	0
T27	2025	0	0	0
T28	854	0	0	0
T32	2363	0	0	0
T71	0	1	0	0
T151	0	2	0	0
T157	0	4	0	0
T200	0	5	0	0
T235	0	1537	0	0
T236	0	3075	0	0
T251	0	1	0	0
T252	0	4	0	0
T253	0	11	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217389195	57518	0	0
T132	2596	0	0	0
T146	1839	0	0	0
T228	1616	0	0	0
T235	167214	1868	0	0
T236	0	3607	0	0
T237	0	4391	0	0
T238	0	667	0	0
T239	0	10231	0	0
T240	0	6179	0	0
T241	0	3498	0	0
T242	0	3593	0	0
T243	0	3298	0	0
T244	0	4098	0	0
T245	7625	0	0	0
T246	2230	0	0	0
T247	2914	0	0	0
T248	5244	0	0	0
T249	1483	0	0	0
T250	5672	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217389195	58934	0	0
T16	2945	0	0	0
T25	5206	0	0	0
T26	1706	0	0	0
T40	494448	0	0	0
T41	270658	0	0	0
T47	1843	0	0	0
T52	14353	100	0	0
T71	0	11	0	0
T73	723	0	0	0
T76	2142	0	0	0
T204	0	67	0	0
T235	0	1730	0	0
T236	0	3235	0	0
T237	0	4350	0	0
T253	0	102	0	0
T254	0	5	0	0
T255	0	83	0	0
T256	0	18	0	0
T257	1826	0	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217389195	51526	0	0
T132	2596	0	0	0
T146	1839	0	0	0
T228	1616	0	0	0
T235	167214	1526	0	0
T236	0	2862	0	0
T237	0	3658	0	0
T238	0	591	0	0
T239	0	9114	0	0
T240	0	5110	0	0
T241	0	3405	0	0
T242	0	3099	0	0
T243	0	2700	0	0
T244	0	3415	0	0
T245	7625	0	0	0
T246	2230	0	0	0
T247	2914	0	0	0
T248	5244	0	0	0
T249	1483	0	0	0
T250	5672	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217389195	60002	0	0
T132	2596	0	0	0
T146	1839	0	0	0
T228	1616	0	0	0
T235	167214	2102	0	0
T236	0	3457	0	0
T237	0	4589	0	0
T238	0	654	0	0
T239	0	9850	0	0
T240	0	6099	0	0
T241	0	3899	0	0
T242	0	3391	0	0
T243	0	2929	0	0
T244	0	4177	0	0
T245	7625	0	0	0
T246	2230	0	0	0
T247	2914	0	0	0
T248	5244	0	0	0
T249	1483	0	0	0
T250	5672	0	0	0