Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.29	98.25	93.91	97.02	92.44	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.21	99.92	92.66	82.54	92.44	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T18,T19,T27

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T21,T22
1	0	Covered	T5,T6,T15

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T19	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T18,T19	Yes	T1,T18,T19	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T18,T19	Yes	T1,T18,T19	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T18,T19	Yes	T1,T18,T19	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T4,T40,T41	Yes	T4,T40,T41	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T18,T19,T27	Yes	T2,T3,T18	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T3,T10	Yes	T1,T3,T10	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T3,T19	Yes	T1,T3,T19	INPUT
edn_i[3].edn_req	Yes	Yes	T3,T5,T10	Yes	T3,T5,T10	INPUT
edn_i[4].edn_req	Yes	Yes	T3,T18,T10	Yes	T3,T18,T10	INPUT
edn_i[5].edn_req	Yes	Yes	T3,T10,T42	Yes	T3,T10,T42	INPUT
edn_i[6].edn_req	Yes	Yes	T3,T10,T42	Yes	T3,T10,T42	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T2,T3,T27	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T2,T4,T10	Yes	T1,T2,T27	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T1,T10,T42	Yes	T1,T3,T10	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T10,T42,T43	Yes	T1,T3,T10	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T1,T3,T10	Yes	T1,T3,T10	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T3,T19	Yes	T1,T3,T19	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T1,T3,T19	Yes	T1,T3,T19	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T3,T19	Yes	T1,T3,T19	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T3,T10,T44	Yes	T3,T10,T44	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T12,T45,T46	Yes	T10,T44,T47	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T3,T5,T10	Yes	T3,T5,T10	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T3,T18,T10	Yes	T3,T18,T10	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T3,T10,T45	Yes	T3,T18,T10	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T3,T18,T10	Yes	T3,T18,T10	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T3,T42,T24	Yes	T3,T42,T11	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T42,T26,T48	Yes	T10,T42,T26	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T3,T10,T42	Yes	T3,T10,T42	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T3,T42,T49	Yes	T3,T10,T42	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T42,T50,T45	Yes	T10,T42,T49	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T3,T10,T42	Yes	T3,T10,T42	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T18,T19,T51	Yes	T18,T19,T51	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T18,T19,T27	Yes	T18,T19,T27	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T5,T6,T15	Yes	T5,T6,T15	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T18,T19,T27	Yes	T18,T19,T27	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T5,T6,T15	Yes	T5,T6,T15	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T52,T40	Yes	T4,T52,T40	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T5,T53	Yes	T4,T5,T53	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	216839667	216660242	0	0
CsrngAppIfOut_A	216839667	216660242	0	0
FpvSecCmCntAlertCheck_A	216839667	109	0	0
FpvSecCmGenCmdFifoRptrCheck_A	216839667	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	216839667	70	0	0
FpvSecCmMainFsmCheck_A	216839667	70	0	0
FpvSecCmRegWeOnehotCheck_A	216839667	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	216839667	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	216839667	70	0	0
IntrEdnCmdReqDoneKnownO_A	216839667	216660242	0	0
TlAReadyKnownO_A	216839667	216660242	0	0
TlDValidKnownO_A	216839667	216660242	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	216839667	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	216839667	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	216839667	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	216839667	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	216839667	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	216839667	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	216839667	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	216839667	577498	0	322
gen_edn_if_asserts[0].EdnDataStable_A	216839667	25465	0	441
gen_edn_if_asserts[0].EdnEndPointOut_A	216839667	216660242	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	216839667	142342	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	216839667	577498	0	322
gen_edn_if_asserts[1].EdnDataStable_A	216839667	4159	0	132
gen_edn_if_asserts[1].EdnEndPointOut_A	216839667	216660242	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	216839667	142342	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	216839667	577498	0	322
gen_edn_if_asserts[2].EdnDataStable_A	216839667	4225	0	124
gen_edn_if_asserts[2].EdnEndPointOut_A	216839667	216660242	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	216839667	142342	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	216839667	577498	0	322
gen_edn_if_asserts[3].EdnDataStable_A	216839667	3453	0	99
gen_edn_if_asserts[3].EdnEndPointOut_A	216839667	216660242	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	216839667	142342	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	216839667	577498	0	322
gen_edn_if_asserts[4].EdnDataStable_A	216839667	3208	0	91
gen_edn_if_asserts[4].EdnEndPointOut_A	216839667	216660242	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	216839667	142342	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	216839667	577498	0	322
gen_edn_if_asserts[5].EdnDataStable_A	216839667	3841	0	96
gen_edn_if_asserts[5].EdnEndPointOut_A	216839667	216660242	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	216839667	142342	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	216839667	577498	0	322
gen_edn_if_asserts[6].EdnDataStable_A	216839667	1947	0	88
gen_edn_if_asserts[6].EdnEndPointOut_A	216839667	216660242	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	216839667	142342	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	216660242	0	0
T1	5270	5219	0	0
T2	7461	7362	0	0
T3	2965	2895	0	0
T4	450859	450845	0	0
T5	1368	1204	0	0
T18	1838	1775	0	0
T19	2559	2475	0	0
T23	2711	2613	0	0
T27	2025	1953	0	0
T28	854	795	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	216660242	0	0
T1	5270	5219	0	0
T2	7461	7362	0	0
T3	2965	2895	0	0
T4	450859	450845	0	0
T5	1368	1204	0	0
T18	1838	1775	0	0
T19	2559	2475	0	0
T23	2711	2613	0	0
T27	2025	1953	0	0
T28	854	795	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	109	0	0
T11	2668	0	0	0
T15	491	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T20	0	20	0	0
T24	1982	0	0	0
T42	2814	0	0	0
T44	2507	0	0	0
T49	984	0	0	0
T51	1924	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	1162	0	0	0
T61	2472	0	0	0
T62	2300	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	70	0	0
T9	1081	0	0	0
T20	47649	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T63	0	10	0	0
T64	0	10	0	0
T65	1098	0	0	0
T66	2156	0	0	0
T67	2127	0	0	0
T68	1810	0	0	0
T69	2338	0	0	0
T70	1802	0	0	0
T71	8809	0	0	0
T72	2548	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	70	0	0
T9	1081	0	0	0
T20	47649	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T63	0	10	0	0
T64	0	10	0	0
T65	1098	0	0	0
T66	2156	0	0	0
T67	2127	0	0	0
T68	1810	0	0	0
T69	2338	0	0	0
T70	1802	0	0	0
T71	8809	0	0	0
T72	2548	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	70	0	0
T9	1081	0	0	0
T20	47649	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T63	0	10	0	0
T64	0	10	0	0
T65	1098	0	0	0
T66	2156	0	0	0
T67	2127	0	0	0
T68	1810	0	0	0
T69	2338	0	0	0
T70	1802	0	0	0
T71	8809	0	0	0
T72	2548	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	70	0	0
T9	1081	0	0	0
T20	47649	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T63	0	10	0	0
T64	0	10	0	0
T65	1098	0	0	0
T66	2156	0	0	0
T67	2127	0	0	0
T68	1810	0	0	0
T69	2338	0	0	0
T70	1802	0	0	0
T71	8809	0	0	0
T72	2548	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	70	0	0
T9	1081	0	0	0
T20	47649	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T63	0	10	0	0
T64	0	10	0	0
T65	1098	0	0	0
T66	2156	0	0	0
T67	2127	0	0	0
T68	1810	0	0	0
T69	2338	0	0	0
T70	1802	0	0	0
T71	8809	0	0	0
T72	2548	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	70	0	0
T9	1081	0	0	0
T20	47649	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T63	0	10	0	0
T64	0	10	0	0
T65	1098	0	0	0
T66	2156	0	0	0
T67	2127	0	0	0
T68	1810	0	0	0
T69	2338	0	0	0
T70	1802	0	0	0
T71	8809	0	0	0
T72	2548	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	216660242	0	0
T1	5270	5219	0	0
T2	7461	7362	0	0
T3	2965	2895	0	0
T4	450859	450845	0	0
T5	1368	1204	0	0
T18	1838	1775	0	0
T19	2559	2475	0	0
T23	2711	2613	0	0
T27	2025	1953	0	0
T28	854	795	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	216660242	0	0
T1	5270	5219	0	0
T2	7461	7362	0	0
T3	2965	2895	0	0
T4	450859	450845	0	0
T5	1368	1204	0	0
T18	1838	1775	0	0
T19	2559	2475	0	0
T23	2711	2613	0	0
T27	2025	1953	0	0
T28	854	795	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	216660242	0	0
T1	5270	5219	0	0
T2	7461	7362	0	0
T3	2965	2895	0	0
T4	450859	450845	0	0
T5	1368	1204	0	0
T18	1838	1775	0	0
T19	2559	2475	0	0
T23	2711	2613	0	0
T27	2025	1953	0	0
T28	854	795	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	70	0	0
T9	1081	0	0	0
T20	47649	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T63	0	10	0	0
T64	0	10	0	0
T65	1098	0	0	0
T66	2156	0	0	0
T67	2127	0	0	0
T68	1810	0	0	0
T69	2338	0	0	0
T70	1802	0	0	0
T71	8809	0	0	0
T72	2548	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	70	0	0
T9	1081	0	0	0
T20	47649	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T63	0	10	0	0
T64	0	10	0	0
T65	1098	0	0	0
T66	2156	0	0	0
T67	2127	0	0	0
T68	1810	0	0	0
T69	2338	0	0	0
T70	1802	0	0	0
T71	8809	0	0	0
T72	2548	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	70	0	0
T9	1081	0	0	0
T20	47649	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T63	0	10	0	0
T64	0	10	0	0
T65	1098	0	0	0
T66	2156	0	0	0
T67	2127	0	0	0
T68	1810	0	0	0
T69	2338	0	0	0
T70	1802	0	0	0
T71	8809	0	0	0
T72	2548	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	70	0	0
T9	1081	0	0	0
T20	47649	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T63	0	10	0	0
T64	0	10	0	0
T65	1098	0	0	0
T66	2156	0	0	0
T67	2127	0	0	0
T68	1810	0	0	0
T69	2338	0	0	0
T70	1802	0	0	0
T71	8809	0	0	0
T72	2548	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	70	0	0
T9	1081	0	0	0
T20	47649	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T63	0	10	0	0
T64	0	10	0	0
T65	1098	0	0	0
T66	2156	0	0	0
T67	2127	0	0	0
T68	1810	0	0	0
T69	2338	0	0	0
T70	1802	0	0	0
T71	8809	0	0	0
T72	2548	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	70	0	0
T9	1081	0	0	0
T20	47649	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T63	0	10	0	0
T64	0	10	0	0
T65	1098	0	0	0
T66	2156	0	0	0
T67	2127	0	0	0
T68	1810	0	0	0
T69	2338	0	0	0
T70	1802	0	0	0
T71	8809	0	0	0
T72	2548	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	70	0	0
T9	1081	0	0	0
T20	47649	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T63	0	10	0	0
T64	0	10	0	0
T65	1098	0	0	0
T66	2156	0	0	0
T67	2127	0	0	0
T68	1810	0	0	0
T69	2338	0	0	0
T70	1802	0	0	0
T71	8809	0	0	0
T72	2548	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	577498	0	322
T1	5270	102	0	0
T2	7461	215	0	0
T3	2965	24	0	0
T4	450859	1443	0	2
T5	1368	531	0	0
T11	0	0	0	2
T18	1838	197	0	0
T19	2559	638	0	0
T23	2711	504	0	0
T24	0	0	0	2
T26	0	0	0	2
T27	2025	218	0	0
T28	854	18	0	0
T40	0	0	0	2
T41	0	0	0	2
T44	0	0	0	2
T47	0	0	0	2
T52	0	0	0	2
T73	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	25465	0	441
T1	5270	3	0	1
T2	7461	671	0	1
T3	2965	3	0	1
T4	450859	92	0	0
T5	1368	0	0	0
T10	0	8	0	1
T18	1838	0	0	0
T19	2559	4	0	1
T23	2711	8	0	1
T27	2025	4	0	1
T28	854	3	0	1
T32	0	4	0	1
T42	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	216660242	0	0
T1	5270	5219	0	0
T2	7461	7362	0	0
T3	2965	2895	0	0
T4	450859	450845	0	0
T5	1368	1204	0	0
T18	1838	1775	0	0
T19	2559	2475	0	0
T23	2711	2613	0	0
T27	2025	1953	0	0
T28	854	795	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	142342	0	0
T5	1368	631	0	0
T6	821	416	0	0
T10	6664	0	0	0
T11	2668	0	0	0
T15	491	214	0	0
T16	0	1145	0	0
T17	0	326	0	0
T28	854	0	0	0
T32	2363	0	0	0
T42	2814	0	0	0
T43	0	1110	0	0
T49	984	0	0	0
T53	0	1111	0	0
T60	1162	0	0	0
T62	0	1144	0	0
T74	0	1100	0	0
T75	0	470	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	577498	0	322
T1	5270	102	0	0
T2	7461	215	0	0
T3	2965	24	0	0
T4	450859	1443	0	2
T5	1368	531	0	0
T11	0	0	0	2
T18	1838	197	0	0
T19	2559	638	0	0
T23	2711	504	0	0
T24	0	0	0	2
T26	0	0	0	2
T27	2025	218	0	0
T28	854	18	0	0
T40	0	0	0	2
T41	0	0	0	2
T44	0	0	0	2
T47	0	0	0	2
T52	0	0	0	2
T73	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	4159	0	132
T1	5270	3	0	1
T2	7461	0	0	0
T3	2965	3	0	1
T4	450859	0	0	0
T5	1368	0	0	0
T10	0	455	0	1
T18	1838	0	0	0
T19	2559	0	0	0
T23	2711	0	0	0
T27	2025	0	0	0
T28	854	0	0	0
T42	0	38	0	1
T43	0	1	0	0
T50	0	4	0	1
T76	0	4	0	1
T77	0	4	0	1
T78	0	4	0	1
T79	0	4	0	1
T80	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	216660242	0	0
T1	5270	5219	0	0
T2	7461	7362	0	0
T3	2965	2895	0	0
T4	450859	450845	0	0
T5	1368	1204	0	0
T18	1838	1775	0	0
T19	2559	2475	0	0
T23	2711	2613	0	0
T27	2025	1953	0	0
T28	854	795	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	142342	0	0
T5	1368	631	0	0
T6	821	416	0	0
T10	6664	0	0	0
T11	2668	0	0	0
T15	491	214	0	0
T16	0	1145	0	0
T17	0	326	0	0
T28	854	0	0	0
T32	2363	0	0	0
T42	2814	0	0	0
T43	0	1110	0	0
T49	984	0	0	0
T53	0	1111	0	0
T60	1162	0	0	0
T62	0	1144	0	0
T74	0	1100	0	0
T75	0	470	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	577498	0	322
T1	5270	102	0	0
T2	7461	215	0	0
T3	2965	24	0	0
T4	450859	1443	0	2
T5	1368	531	0	0
T11	0	0	0	2
T18	1838	197	0	0
T19	2559	638	0	0
T23	2711	504	0	0
T24	0	0	0	2
T26	0	0	0	2
T27	2025	218	0	0
T28	854	18	0	0
T40	0	0	0	2
T41	0	0	0	2
T44	0	0	0	2
T47	0	0	0	2
T52	0	0	0	2
T73	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	4225	0	124
T1	5270	47	0	1
T2	7461	0	0	0
T3	2965	28	0	1
T4	450859	0	0	0
T5	1368	0	0	0
T10	0	42	0	1
T12	0	0	0	1
T18	1838	0	0	0
T19	2559	4	0	0
T23	2711	0	0	0
T27	2025	0	0	0
T28	854	0	0	0
T32	0	4	0	0
T42	0	3	0	1
T47	0	4	0	0
T51	0	4	0	1
T74	0	1	0	0
T80	0	0	0	1
T81	0	3	0	1
T82	0	0	0	1
T83	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	216660242	0	0
T1	5270	5219	0	0
T2	7461	7362	0	0
T3	2965	2895	0	0
T4	450859	450845	0	0
T5	1368	1204	0	0
T18	1838	1775	0	0
T19	2559	2475	0	0
T23	2711	2613	0	0
T27	2025	1953	0	0
T28	854	795	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	142342	0	0
T5	1368	631	0	0
T6	821	416	0	0
T10	6664	0	0	0
T11	2668	0	0	0
T15	491	214	0	0
T16	0	1145	0	0
T17	0	326	0	0
T28	854	0	0	0
T32	2363	0	0	0
T42	2814	0	0	0
T43	0	1110	0	0
T49	984	0	0	0
T53	0	1111	0	0
T60	1162	0	0	0
T62	0	1144	0	0
T74	0	1100	0	0
T75	0	470	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	577498	0	322
T1	5270	102	0	0
T2	7461	215	0	0
T3	2965	24	0	0
T4	450859	1443	0	2
T5	1368	531	0	0
T11	0	0	0	2
T18	1838	197	0	0
T19	2559	638	0	0
T23	2711	504	0	0
T24	0	0	0	2
T26	0	0	0	2
T27	2025	218	0	0
T28	854	18	0	0
T40	0	0	0	2
T41	0	0	0	2
T44	0	0	0	2
T47	0	0	0	2
T52	0	0	0	2
T73	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	3453	0	99
T3	2965	11	0	1
T4	450859	0	0	0
T5	1368	1	0	0
T10	6664	3	0	1
T12	0	0	0	1
T18	1838	0	0	0
T19	2559	0	0	0
T23	2711	0	0	0
T27	2025	0	0	0
T28	854	0	0	0
T32	2363	0	0	0
T44	0	4	0	0
T45	0	0	0	1
T46	0	0	0	1
T47	0	1	0	0
T53	0	1	0	0
T68	0	0	0	1
T80	0	3	0	1
T84	0	3	0	1
T85	0	4	0	1
T86	0	4	0	0
T87	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	216660242	0	0
T1	5270	5219	0	0
T2	7461	7362	0	0
T3	2965	2895	0	0
T4	450859	450845	0	0
T5	1368	1204	0	0
T18	1838	1775	0	0
T19	2559	2475	0	0
T23	2711	2613	0	0
T27	2025	1953	0	0
T28	854	795	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	142342	0	0
T5	1368	631	0	0
T6	821	416	0	0
T10	6664	0	0	0
T11	2668	0	0	0
T15	491	214	0	0
T16	0	1145	0	0
T17	0	326	0	0
T28	854	0	0	0
T32	2363	0	0	0
T42	2814	0	0	0
T43	0	1110	0	0
T49	984	0	0	0
T53	0	1111	0	0
T60	1162	0	0	0
T62	0	1144	0	0
T74	0	1100	0	0
T75	0	470	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	577498	0	322
T1	5270	102	0	0
T2	7461	215	0	0
T3	2965	24	0	0
T4	450859	1443	0	2
T5	1368	531	0	0
T11	0	0	0	2
T18	1838	197	0	0
T19	2559	638	0	0
T23	2711	504	0	0
T24	0	0	0	2
T26	0	0	0	2
T27	2025	218	0	0
T28	854	18	0	0
T40	0	0	0	2
T41	0	0	0	2
T44	0	0	0	2
T47	0	0	0	2
T52	0	0	0	2
T73	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	3208	0	91
T3	2965	14	0	1
T4	450859	0	0	0
T5	1368	0	0	0
T10	6664	25	0	1
T12	0	3	0	1
T18	1838	4	0	1
T19	2559	0	0	0
T23	2711	0	0	0
T27	2025	0	0	0
T28	854	0	0	0
T32	2363	0	0	0
T42	0	3	0	1
T45	0	16	0	1
T46	0	3	0	1
T68	0	4	0	0
T80	0	3	0	1
T88	0	4	0	1
T89	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	216660242	0	0
T1	5270	5219	0	0
T2	7461	7362	0	0
T3	2965	2895	0	0
T4	450859	450845	0	0
T5	1368	1204	0	0
T18	1838	1775	0	0
T19	2559	2475	0	0
T23	2711	2613	0	0
T27	2025	1953	0	0
T28	854	795	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	142342	0	0
T5	1368	631	0	0
T6	821	416	0	0
T10	6664	0	0	0
T11	2668	0	0	0
T15	491	214	0	0
T16	0	1145	0	0
T17	0	326	0	0
T28	854	0	0	0
T32	2363	0	0	0
T42	2814	0	0	0
T43	0	1110	0	0
T49	984	0	0	0
T53	0	1111	0	0
T60	1162	0	0	0
T62	0	1144	0	0
T74	0	1100	0	0
T75	0	470	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	577498	0	322
T1	5270	102	0	0
T2	7461	215	0	0
T3	2965	24	0	0
T4	450859	1443	0	2
T5	1368	531	0	0
T11	0	0	0	2
T18	1838	197	0	0
T19	2559	638	0	0
T23	2711	504	0	0
T24	0	0	0	2
T26	0	0	0	2
T27	2025	218	0	0
T28	854	18	0	0
T40	0	0	0	2
T41	0	0	0	2
T44	0	0	0	2
T47	0	0	0	2
T52	0	0	0	2
T73	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	3841	0	96
T3	2965	3	0	1
T4	450859	0	0	0
T5	1368	0	0	0
T10	6664	3	0	1
T11	0	4	0	0
T18	1838	0	0	0
T19	2559	0	0	0
T23	2711	0	0	0
T24	0	4	0	0
T26	0	4	0	0
T27	2025	0	0	0
T28	854	0	0	0
T32	2363	0	0	0
T42	0	27	0	1
T45	0	0	0	1
T48	0	615	0	1
T80	0	0	0	1
T90	0	4	0	1
T91	0	4	0	1
T92	0	3	0	1
T93	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	216660242	0	0
T1	5270	5219	0	0
T2	7461	7362	0	0
T3	2965	2895	0	0
T4	450859	450845	0	0
T5	1368	1204	0	0
T18	1838	1775	0	0
T19	2559	2475	0	0
T23	2711	2613	0	0
T27	2025	1953	0	0
T28	854	795	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	142342	0	0
T5	1368	631	0	0
T6	821	416	0	0
T10	6664	0	0	0
T11	2668	0	0	0
T15	491	214	0	0
T16	0	1145	0	0
T17	0	326	0	0
T28	854	0	0	0
T32	2363	0	0	0
T42	2814	0	0	0
T43	0	1110	0	0
T49	984	0	0	0
T53	0	1111	0	0
T60	1162	0	0	0
T62	0	1144	0	0
T74	0	1100	0	0
T75	0	470	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	577498	0	322
T1	5270	102	0	0
T2	7461	215	0	0
T3	2965	24	0	0
T4	450859	1443	0	2
T5	1368	531	0	0
T11	0	0	0	2
T18	1838	197	0	0
T19	2559	638	0	0
T23	2711	504	0	0
T24	0	0	0	2
T26	0	0	0	2
T27	2025	218	0	0
T28	854	18	0	0
T40	0	0	0	2
T41	0	0	0	2
T44	0	0	0	2
T47	0	0	0	2
T52	0	0	0	2
T73	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	1947	0	88
T3	2965	3	0	1
T4	450859	0	0	0
T5	1368	0	0	0
T10	6664	3	0	1
T12	0	3	0	1
T18	1838	0	0	0
T19	2559	0	0	0
T23	2711	0	0	0
T26	0	4	0	0
T27	2025	0	0	0
T28	854	0	0	0
T32	2363	0	0	0
T42	0	49	0	1
T45	0	63	0	1
T46	0	3	0	1
T49	0	3	0	1
T50	0	4	0	0
T94	0	3	0	1
T95	0	0	0	1
T96	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	216660242	0	0
T1	5270	5219	0	0
T2	7461	7362	0	0
T3	2965	2895	0	0
T4	450859	450845	0	0
T5	1368	1204	0	0
T18	1838	1775	0	0
T19	2559	2475	0	0
T23	2711	2613	0	0
T27	2025	1953	0	0
T28	854	795	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216839667	142342	0	0
T5	1368	631	0	0
T6	821	416	0	0
T10	6664	0	0	0
T11	2668	0	0	0
T15	491	214	0	0
T16	0	1145	0	0
T17	0	326	0	0
T28	854	0	0	0
T32	2363	0	0	0
T42	2814	0	0	0
T43	0	1110	0	0
T49	984	0	0	0
T53	0	1111	0	0
T60	1162	0	0	0
T62	0	1144	0	0
T74	0	1100	0	0
T75	0	470	0	0