Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.21	98.25	93.97	97.02	91.86	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.13	99.92	92.75	82.54	91.86	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T26,T8

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T19
1	0	Covered	T1,T40,T41

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T26,T8	Yes	T3,T26,T8	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T3,T4,T45	Yes	T3,T4,T45	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T26	Yes	T2,T3,T26	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T28,T21,T22	Yes	T28,T21,T22	INPUT
edn_i[2].edn_req	Yes	Yes	T10,T23,T46	Yes	T10,T23,T46	INPUT
edn_i[3].edn_req	Yes	Yes	T10,T20,T47	Yes	T10,T20,T47	INPUT
edn_i[4].edn_req	Yes	Yes	T10,T46,T48	Yes	T10,T46,T48	INPUT
edn_i[5].edn_req	Yes	Yes	T49,T47,T50	Yes	T49,T47,T50	INPUT
edn_i[6].edn_req	Yes	Yes	T21,T51,T52	Yes	T21,T51,T52	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T3,T26,T8	Yes	T2,T3,T26	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T3,T29,T9	Yes	T3,T26,T29	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T2,T3,T26	Yes	T2,T3,T26	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T28,T21,T23	Yes	T28,T21,T22	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T47,T53,T24	Yes	T28,T54,T47	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T28,T21,T22	Yes	T28,T21,T22	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T10,T46,T5	Yes	T10,T46,T5	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T46,T5,T47	Yes	T10,T23,T46	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T10,T23,T46	Yes	T10,T23,T46	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T10,T20,T47	Yes	T10,T20,T47	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T10,T50,T25	Yes	T10,T50,T25	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T10,T20,T47	Yes	T10,T20,T47	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T48,T55,T25	Yes	T10,T46,T48	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T56,T57,T58	Yes	T10,T48,T55	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T10,T46,T48	Yes	T10,T46,T48	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T49,T47,T50	Yes	T49,T47,T50	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T50,T59,T57	Yes	T47,T50,T24	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T49,T47,T50	Yes	T49,T47,T50	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T21,T51,T52	Yes	T21,T51,T52	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T21,T47,T60	Yes	T21,T47,T61	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T21,T51,T52	Yes	T21,T51,T52	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T3,T29,T10	Yes	T3,T29,T10	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T3,T8,T29	Yes	T3,T29,T10	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T2,T3,T26	Yes	T2,T3,T26	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T2,T28,T62	Yes	T2,T28,T62	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T26,T8	Yes	T2,T26,T8	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T27,T30	Yes	T1,T27,T30	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T26,T8	Yes	T2,T26,T8	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T27,T30	Yes	T1,T27,T30	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T3,T4,T45	Yes	T3,T4,T45	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T3,T4,T45	Yes	T3,T4,T45	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	238436454	238237985	0	0
CsrngAppIfOut_A	238436454	238237985	0	0
FpvSecCmCntAlertCheck_A	238436454	124	0	0
FpvSecCmGenCmdFifoRptrCheck_A	238436454	90	0	0
FpvSecCmGenCmdFifoWptrCheck_A	238436454	90	0	0
FpvSecCmMainFsmCheck_A	238436454	90	0	0
FpvSecCmRegWeOnehotCheck_A	238436454	90	0	0
FpvSecCmResCmdFifoRptrCheck_A	238436454	90	0	0
FpvSecCmResCmdFifoWptrCheck_A	238436454	90	0	0
IntrEdnCmdReqDoneKnownO_A	238436454	238237985	0	0
TlAReadyKnownO_A	238436454	238237985	0	0
TlDValidKnownO_A	238436454	238237985	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	238436454	90	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	238436454	90	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	238436454	90	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	238436454	90	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	238436454	90	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	238436454	90	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	238436454	90	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	238436454	597248	0	324
gen_edn_if_asserts[0].EdnDataStable_A	238436454	120363	0	417
gen_edn_if_asserts[0].EdnEndPointOut_A	238436454	238237985	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	238436454	159384	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	238436454	597248	0	324
gen_edn_if_asserts[1].EdnDataStable_A	238436454	5481	0	134
gen_edn_if_asserts[1].EdnEndPointOut_A	238436454	238237985	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	238436454	159384	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	238436454	597248	0	324
gen_edn_if_asserts[2].EdnDataStable_A	238436454	7776	0	132
gen_edn_if_asserts[2].EdnEndPointOut_A	238436454	238237985	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	238436454	159384	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	238436454	597248	0	324
gen_edn_if_asserts[3].EdnDataStable_A	238436454	4322	0	112
gen_edn_if_asserts[3].EdnEndPointOut_A	238436454	238237985	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	238436454	159384	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	238436454	597248	0	324
gen_edn_if_asserts[4].EdnDataStable_A	238436454	5288	0	109
gen_edn_if_asserts[4].EdnEndPointOut_A	238436454	238237985	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	238436454	159384	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	238436454	597248	0	324
gen_edn_if_asserts[5].EdnDataStable_A	238436454	3824	0	100
gen_edn_if_asserts[5].EdnEndPointOut_A	238436454	238237985	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	238436454	159384	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	238436454	597248	0	324
gen_edn_if_asserts[6].EdnDataStable_A	238436454	3380	0	83
gen_edn_if_asserts[6].EdnEndPointOut_A	238436454	238237985	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	238436454	159384	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	238237985	0	0
T1	1894	1727	0	0
T2	2104	2009	0	0
T3	194539	194530	0	0
T8	2052	2000	0	0
T9	1799	1718	0	0
T26	2400	2327	0	0
T27	2212	2119	0	0
T28	2324	2226	0	0
T29	2316	2223	0	0
T30	2937	2849	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	238237985	0	0
T1	1894	1727	0	0
T2	2104	2009	0	0
T3	194539	194530	0	0
T8	2052	2000	0	0
T9	1799	1718	0	0
T26	2400	2327	0	0
T27	2212	2119	0	0
T28	2324	2226	0	0
T29	2316	2223	0	0
T30	2937	2849	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	124	0	0
T12	3817	0	0	0
T14	757	1	0	0
T15	763	1	0	0
T16	0	1	0	0
T17	0	10	0	0
T18	0	20	0	0
T47	2124	0	0	0
T50	2109	0	0	0
T53	1896	0	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	1948	0	0	0
T69	2139	0	0	0
T70	1865	0	0	0
T71	786269	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	90	0	0
T17	25432	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T43	2558	0	0	0
T72	0	20	0	0
T73	0	20	0	0
T74	4101	0	0	0
T75	3362	0	0	0
T76	3777	0	0	0
T77	802	0	0	0
T78	10284	0	0	0
T79	776	0	0	0
T80	1828	0	0	0
T81	1674	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	90	0	0
T17	25432	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T43	2558	0	0	0
T72	0	20	0	0
T73	0	20	0	0
T74	4101	0	0	0
T75	3362	0	0	0
T76	3777	0	0	0
T77	802	0	0	0
T78	10284	0	0	0
T79	776	0	0	0
T80	1828	0	0	0
T81	1674	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	90	0	0
T17	25432	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T43	2558	0	0	0
T72	0	20	0	0
T73	0	20	0	0
T74	4101	0	0	0
T75	3362	0	0	0
T76	3777	0	0	0
T77	802	0	0	0
T78	10284	0	0	0
T79	776	0	0	0
T80	1828	0	0	0
T81	1674	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	90	0	0
T17	25432	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T43	2558	0	0	0
T72	0	20	0	0
T73	0	20	0	0
T74	4101	0	0	0
T75	3362	0	0	0
T76	3777	0	0	0
T77	802	0	0	0
T78	10284	0	0	0
T79	776	0	0	0
T80	1828	0	0	0
T81	1674	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	90	0	0
T17	25432	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T43	2558	0	0	0
T72	0	20	0	0
T73	0	20	0	0
T74	4101	0	0	0
T75	3362	0	0	0
T76	3777	0	0	0
T77	802	0	0	0
T78	10284	0	0	0
T79	776	0	0	0
T80	1828	0	0	0
T81	1674	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	90	0	0
T17	25432	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T43	2558	0	0	0
T72	0	20	0	0
T73	0	20	0	0
T74	4101	0	0	0
T75	3362	0	0	0
T76	3777	0	0	0
T77	802	0	0	0
T78	10284	0	0	0
T79	776	0	0	0
T80	1828	0	0	0
T81	1674	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	238237985	0	0
T1	1894	1727	0	0
T2	2104	2009	0	0
T3	194539	194530	0	0
T8	2052	2000	0	0
T9	1799	1718	0	0
T26	2400	2327	0	0
T27	2212	2119	0	0
T28	2324	2226	0	0
T29	2316	2223	0	0
T30	2937	2849	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	238237985	0	0
T1	1894	1727	0	0
T2	2104	2009	0	0
T3	194539	194530	0	0
T8	2052	2000	0	0
T9	1799	1718	0	0
T26	2400	2327	0	0
T27	2212	2119	0	0
T28	2324	2226	0	0
T29	2316	2223	0	0
T30	2937	2849	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	238237985	0	0
T1	1894	1727	0	0
T2	2104	2009	0	0
T3	194539	194530	0	0
T8	2052	2000	0	0
T9	1799	1718	0	0
T26	2400	2327	0	0
T27	2212	2119	0	0
T28	2324	2226	0	0
T29	2316	2223	0	0
T30	2937	2849	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	90	0	0
T17	25432	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T43	2558	0	0	0
T72	0	20	0	0
T73	0	20	0	0
T74	4101	0	0	0
T75	3362	0	0	0
T76	3777	0	0	0
T77	802	0	0	0
T78	10284	0	0	0
T79	776	0	0	0
T80	1828	0	0	0
T81	1674	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	90	0	0
T17	25432	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T43	2558	0	0	0
T72	0	20	0	0
T73	0	20	0	0
T74	4101	0	0	0
T75	3362	0	0	0
T76	3777	0	0	0
T77	802	0	0	0
T78	10284	0	0	0
T79	776	0	0	0
T80	1828	0	0	0
T81	1674	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	90	0	0
T17	25432	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T43	2558	0	0	0
T72	0	20	0	0
T73	0	20	0	0
T74	4101	0	0	0
T75	3362	0	0	0
T76	3777	0	0	0
T77	802	0	0	0
T78	10284	0	0	0
T79	776	0	0	0
T80	1828	0	0	0
T81	1674	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	90	0	0
T17	25432	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T43	2558	0	0	0
T72	0	20	0	0
T73	0	20	0	0
T74	4101	0	0	0
T75	3362	0	0	0
T76	3777	0	0	0
T77	802	0	0	0
T78	10284	0	0	0
T79	776	0	0	0
T80	1828	0	0	0
T81	1674	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	90	0	0
T17	25432	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T43	2558	0	0	0
T72	0	20	0	0
T73	0	20	0	0
T74	4101	0	0	0
T75	3362	0	0	0
T76	3777	0	0	0
T77	802	0	0	0
T78	10284	0	0	0
T79	776	0	0	0
T80	1828	0	0	0
T81	1674	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	90	0	0
T17	25432	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T43	2558	0	0	0
T72	0	20	0	0
T73	0	20	0	0
T74	4101	0	0	0
T75	3362	0	0	0
T76	3777	0	0	0
T77	802	0	0	0
T78	10284	0	0	0
T79	776	0	0	0
T80	1828	0	0	0
T81	1674	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	90	0	0
T17	25432	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T43	2558	0	0	0
T72	0	20	0	0
T73	0	20	0	0
T74	4101	0	0	0
T75	3362	0	0	0
T76	3777	0	0	0
T77	802	0	0	0
T78	10284	0	0	0
T79	776	0	0	0
T80	1828	0	0	0
T81	1674	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	597248	0	324
T1	1894	1089	0	0
T2	2104	269	0	0
T3	194539	1683	0	2
T4	0	0	0	2
T8	2052	375	0	0
T9	1799	305	0	0
T20	0	0	0	2
T22	0	0	0	2
T23	0	0	0	2
T26	2400	218	0	0
T27	2212	2117	0	2
T28	2324	149	0	0
T29	2316	12	0	0
T30	2937	2847	0	2
T45	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	120363	0	417
T2	2104	4	0	1
T3	194539	87	0	0
T4	0	102	0	0
T8	2052	4	0	1
T9	1799	8	0	1
T10	2022	0	0	0
T26	2400	4	0	1
T27	2212	0	0	0
T28	2324	0	0	0
T29	2316	57	0	1
T30	2937	0	0	0
T45	0	109	0	0
T62	0	4	0	1
T84	0	3	0	1
T85	0	0	0	1
T86	0	0	0	1
T87	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	238237985	0	0
T1	1894	1727	0	0
T2	2104	2009	0	0
T3	194539	194530	0	0
T8	2052	2000	0	0
T9	1799	1718	0	0
T26	2400	2327	0	0
T27	2212	2119	0	0
T28	2324	2226	0	0
T29	2316	2223	0	0
T30	2937	2849	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	159384	0	0
T1	1894	1062	0	0
T2	2104	0	0	0
T3	194539	0	0	0
T5	0	1072	0	0
T8	2052	0	0	0
T9	1799	0	0	0
T14	0	354	0	0
T15	0	418	0	0
T26	2400	0	0	0
T27	2212	0	0	0
T28	2324	0	0	0
T29	2316	0	0	0
T30	2937	0	0	0
T37	0	27	0	0
T40	0	992	0	0
T41	0	272	0	0
T68	0	1138	0	0
T88	0	424	0	0
T89	0	377	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	597248	0	324
T1	1894	1089	0	0
T2	2104	269	0	0
T3	194539	1683	0	2
T4	0	0	0	2
T8	2052	375	0	0
T9	1799	305	0	0
T20	0	0	0	2
T22	0	0	0	2
T23	0	0	0	2
T26	2400	218	0	0
T27	2212	2117	0	2
T28	2324	149	0	0
T29	2316	12	0	0
T30	2937	2847	0	2
T45	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	5481	0	134
T4	269568	0	0	0
T9	1799	0	0	0
T10	2022	0	0	0
T20	2177	0	0	0
T21	0	4	0	1
T22	0	4	0	0
T23	0	4	0	0
T24	0	0	0	1
T28	2324	4	0	1
T29	2316	0	0	0
T30	2937	0	0	0
T40	1854	0	0	0
T45	674367	0	0	0
T47	0	21	0	1
T48	0	3	0	1
T53	0	4	0	0
T54	0	3	0	1
T56	0	0	0	1
T84	1178	0	0	0
T90	0	3	0	1
T91	0	4	0	0
T92	0	0	0	1
T93	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	238237985	0	0
T1	1894	1727	0	0
T2	2104	2009	0	0
T3	194539	194530	0	0
T8	2052	2000	0	0
T9	1799	1718	0	0
T26	2400	2327	0	0
T27	2212	2119	0	0
T28	2324	2226	0	0
T29	2316	2223	0	0
T30	2937	2849	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	159384	0	0
T1	1894	1062	0	0
T2	2104	0	0	0
T3	194539	0	0	0
T5	0	1072	0	0
T8	2052	0	0	0
T9	1799	0	0	0
T14	0	354	0	0
T15	0	418	0	0
T26	2400	0	0	0
T27	2212	0	0	0
T28	2324	0	0	0
T29	2316	0	0	0
T30	2937	0	0	0
T37	0	27	0	0
T40	0	992	0	0
T41	0	272	0	0
T68	0	1138	0	0
T88	0	424	0	0
T89	0	377	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	597248	0	324
T1	1894	1089	0	0
T2	2104	269	0	0
T3	194539	1683	0	2
T4	0	0	0	2
T8	2052	375	0	0
T9	1799	305	0	0
T20	0	0	0	2
T22	0	0	0	2
T23	0	0	0	2
T26	2400	218	0	0
T27	2212	2117	0	2
T28	2324	149	0	0
T29	2316	12	0	0
T30	2937	2847	0	2
T45	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	7776	0	132
T4	269568	0	0	0
T10	2022	15	0	1
T20	2177	0	0	0
T21	1747	0	0	0
T22	1860	0	0	0
T23	0	1	0	0
T25	0	1083	0	1
T40	1854	0	0	0
T45	674367	0	0	0
T46	0	52	0	1
T47	0	42	0	1
T48	0	3	0	1
T59	0	0	0	1
T61	0	3	0	1
T62	2032	0	0	0
T84	1178	0	0	0
T85	10052	0	0	0
T93	0	26	0	1
T94	0	4	0	1
T95	0	4	0	0
T96	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	238237985	0	0
T1	1894	1727	0	0
T2	2104	2009	0	0
T3	194539	194530	0	0
T8	2052	2000	0	0
T9	1799	1718	0	0
T26	2400	2327	0	0
T27	2212	2119	0	0
T28	2324	2226	0	0
T29	2316	2223	0	0
T30	2937	2849	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	159384	0	0
T1	1894	1062	0	0
T2	2104	0	0	0
T3	194539	0	0	0
T5	0	1072	0	0
T8	2052	0	0	0
T9	1799	0	0	0
T14	0	354	0	0
T15	0	418	0	0
T26	2400	0	0	0
T27	2212	0	0	0
T28	2324	0	0	0
T29	2316	0	0	0
T30	2937	0	0	0
T37	0	27	0	0
T40	0	992	0	0
T41	0	272	0	0
T68	0	1138	0	0
T88	0	424	0	0
T89	0	377	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	597248	0	324
T1	1894	1089	0	0
T2	2104	269	0	0
T3	194539	1683	0	2
T4	0	0	0	2
T8	2052	375	0	0
T9	1799	305	0	0
T20	0	0	0	2
T22	0	0	0	2
T23	0	0	0	2
T26	2400	218	0	0
T27	2212	2117	0	2
T28	2324	149	0	0
T29	2316	12	0	0
T30	2937	2847	0	2
T45	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	4322	0	112
T4	269568	0	0	0
T10	2022	30	0	1
T20	2177	4	0	0
T21	1747	0	0	0
T22	1860	0	0	0
T24	0	3	0	1
T25	0	25	0	1
T40	1854	0	0	0
T45	674367	0	0	0
T47	0	3	0	1
T50	0	43	0	1
T57	0	0	0	1
T59	0	17	0	1
T61	0	29	0	1
T62	2032	0	0	0
T84	1178	0	0	0
T85	10052	0	0	0
T93	0	3	0	1
T97	0	4	0	0
T98	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	238237985	0	0
T1	1894	1727	0	0
T2	2104	2009	0	0
T3	194539	194530	0	0
T8	2052	2000	0	0
T9	1799	1718	0	0
T26	2400	2327	0	0
T27	2212	2119	0	0
T28	2324	2226	0	0
T29	2316	2223	0	0
T30	2937	2849	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	159384	0	0
T1	1894	1062	0	0
T2	2104	0	0	0
T3	194539	0	0	0
T5	0	1072	0	0
T8	2052	0	0	0
T9	1799	0	0	0
T14	0	354	0	0
T15	0	418	0	0
T26	2400	0	0	0
T27	2212	0	0	0
T28	2324	0	0	0
T29	2316	0	0	0
T30	2937	0	0	0
T37	0	27	0	0
T40	0	992	0	0
T41	0	272	0	0
T68	0	1138	0	0
T88	0	424	0	0
T89	0	377	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	597248	0	324
T1	1894	1089	0	0
T2	2104	269	0	0
T3	194539	1683	0	2
T4	0	0	0	2
T8	2052	375	0	0
T9	1799	305	0	0
T20	0	0	0	2
T22	0	0	0	2
T23	0	0	0	2
T26	2400	218	0	0
T27	2212	2117	0	2
T28	2324	149	0	0
T29	2316	12	0	0
T30	2937	2847	0	2
T45	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	5288	0	109
T4	269568	0	0	0
T10	2022	3	0	1
T20	2177	0	0	0
T21	1747	0	0	0
T22	1860	0	0	0
T25	0	9	0	1
T35	0	1	0	0
T40	1854	0	0	0
T45	674367	0	0	0
T46	0	3	0	1
T48	0	11	0	1
T55	0	4	0	1
T56	0	15	0	1
T59	0	0	0	1
T61	0	3	0	1
T62	2032	0	0	0
T84	1178	0	0	0
T85	10052	0	0	0
T93	0	3	0	1
T99	0	4	0	0
T100	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	238237985	0	0
T1	1894	1727	0	0
T2	2104	2009	0	0
T3	194539	194530	0	0
T8	2052	2000	0	0
T9	1799	1718	0	0
T26	2400	2327	0	0
T27	2212	2119	0	0
T28	2324	2226	0	0
T29	2316	2223	0	0
T30	2937	2849	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	159384	0	0
T1	1894	1062	0	0
T2	2104	0	0	0
T3	194539	0	0	0
T5	0	1072	0	0
T8	2052	0	0	0
T9	1799	0	0	0
T14	0	354	0	0
T15	0	418	0	0
T26	2400	0	0	0
T27	2212	0	0	0
T28	2324	0	0	0
T29	2316	0	0	0
T30	2937	0	0	0
T37	0	27	0	0
T40	0	992	0	0
T41	0	272	0	0
T68	0	1138	0	0
T88	0	424	0	0
T89	0	377	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	597248	0	324
T1	1894	1089	0	0
T2	2104	269	0	0
T3	194539	1683	0	2
T4	0	0	0	2
T8	2052	375	0	0
T9	1799	305	0	0
T20	0	0	0	2
T22	0	0	0	2
T23	0	0	0	2
T26	2400	218	0	0
T27	2212	2117	0	2
T28	2324	149	0	0
T29	2316	12	0	0
T30	2937	2847	0	2
T45	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	3824	0	100
T13	0	0	0	1
T14	757	0	0	0
T24	0	3	0	1
T47	2124	6	0	1
T48	1966	0	0	0
T49	2642	4	0	0
T50	0	13	0	1
T55	2008	0	0	0
T57	0	27	0	1
T59	0	36	0	1
T60	0	49	0	1
T68	1948	0	0	0
T88	940	0	0	0
T89	740	0	0	0
T101	0	4	0	1
T102	0	12	0	1
T103	0	3	0	1
T104	2054	0	0	0
T105	4884	0	0	0

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	238237985	0	0
T1	1894	1727	0	0
T2	2104	2009	0	0
T3	194539	194530	0	0
T8	2052	2000	0	0
T9	1799	1718	0	0
T26	2400	2327	0	0
T27	2212	2119	0	0
T28	2324	2226	0	0
T29	2316	2223	0	0
T30	2937	2849	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	159384	0	0
T1	1894	1062	0	0
T2	2104	0	0	0
T3	194539	0	0	0
T5	0	1072	0	0
T8	2052	0	0	0
T9	1799	0	0	0
T14	0	354	0	0
T15	0	418	0	0
T26	2400	0	0	0
T27	2212	0	0	0
T28	2324	0	0	0
T29	2316	0	0	0
T30	2937	0	0	0
T37	0	27	0	0
T40	0	992	0	0
T41	0	272	0	0
T68	0	1138	0	0
T88	0	424	0	0
T89	0	377	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	597248	0	324
T1	1894	1089	0	0
T2	2104	269	0	0
T3	194539	1683	0	2
T4	0	0	0	2
T8	2052	375	0	0
T9	1799	305	0	0
T20	0	0	0	2
T22	0	0	0	2
T23	0	0	0	2
T26	2400	218	0	0
T27	2212	2117	0	2
T28	2324	149	0	0
T29	2316	12	0	0
T30	2937	2847	0	2
T45	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	3380	0	83
T21	1747	4	0	0
T22	1860	0	0	0
T23	3949	0	0	0
T41	597	0	0	0
T46	1960	0	0	0
T47	0	35	0	1
T51	2543	4	0	1
T52	0	4	0	0
T57	0	3	0	1
T60	0	61	0	1
T61	0	3	0	1
T62	2032	0	0	0
T85	10052	0	0	0
T86	1470	0	0	0
T87	2774	0	0	0
T91	0	4	0	1
T93	0	3	0	1
T102	0	0	0	1
T103	0	0	0	1
T106	0	3	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	238237985	0	0
T1	1894	1727	0	0
T2	2104	2009	0	0
T3	194539	194530	0	0
T8	2052	2000	0	0
T9	1799	1718	0	0
T26	2400	2327	0	0
T27	2212	2119	0	0
T28	2324	2226	0	0
T29	2316	2223	0	0
T30	2937	2849	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238436454	159384	0	0
T1	1894	1062	0	0
T2	2104	0	0	0
T3	194539	0	0	0
T5	0	1072	0	0
T8	2052	0	0	0
T9	1799	0	0	0
T14	0	354	0	0
T15	0	418	0	0
T26	2400	0	0	0
T27	2212	0	0	0
T28	2324	0	0	0
T29	2316	0	0	0
T30	2937	0	0	0
T37	0	27	0	0
T40	0	992	0	0
T41	0	272	0	0
T68	0	1138	0	0
T88	0	424	0	0
T89	0	377	0	0