Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	238904474	10351551	0	0
boot_gen_cmd_rd_A	238904474	60455	0	0
boot_ins_cmd_rd_A	238904474	70213	0	0
ctrl_rd_A	238904474	61679	0	0
err_code_test_rd_A	238904474	70571	0	0
intr_enable_rd_A	238904474	66775	0	0
max_num_reqs_between_reseeds_rd_A	238904474	62060	0	0
regwen_rd_A	238904474	71176	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238904474	10351551	0	0
T3	194539	78247	0	0
T4	0	150846	0	0
T8	2052	0	0	0
T9	1799	0	0	0
T10	2022	0	0	0
T20	2177	0	0	0
T26	2400	0	0	0
T27	2212	0	0	0
T28	2324	0	0	0
T29	2316	0	0	0
T30	2937	0	0	0
T45	0	383099	0	0
T71	0	443544	0	0
T228	0	201151	0	0
T229	0	262326	0	0
T230	0	71355	0	0
T231	0	118510	0	0
T232	0	80084	0	0
T233	0	375681	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238904474	60455	0	0
T135	3055	0	0	0
T140	759	0	0	0
T173	2858	0	0	0
T213	1816	0	0	0
T231	346052	3529	0	0
T232	205483	0	0	0
T233	0	10814	0	0
T234	0	1461	0	0
T235	0	3212	0	0
T236	0	6738	0	0
T237	0	2937	0	0
T238	0	1809	0	0
T239	0	4582	0	0
T240	0	5860	0	0
T241	0	2126	0	0
T242	1713	0	0	0
T243	1872	0	0	0
T244	3071	0	0	0
T245	7058	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238904474	70213	0	0
T135	3055	0	0	0
T140	759	0	0	0
T173	2858	0	0	0
T213	1816	0	0	0
T231	346052	3914	0	0
T232	205483	0	0	0
T233	0	12510	0	0
T234	0	1858	0	0
T235	0	3530	0	0
T236	0	8069	0	0
T237	0	3558	0	0
T238	0	2017	0	0
T239	0	5522	0	0
T240	0	6814	0	0
T241	0	2510	0	0
T242	1713	0	0	0
T243	1872	0	0	0
T244	3071	0	0	0
T245	7058	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238904474	61679	0	0
T36	2133	3	0	0
T64	915	0	0	0
T65	1339	0	0	0
T103	6342	0	0	0
T195	1170	0	0	0
T215	1901	0	0	0
T228	353970	0	0	0
T229	463620	0	0	0
T231	0	3341	0	0
T233	0	11194	0	0
T234	0	1472	0	0
T235	0	3113	0	0
T246	0	1	0	0
T247	0	7	0	0
T248	0	6	0	0
T249	0	4	0	0
T250	0	8	0	0
T251	1607	0	0	0
T252	1527	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238904474	70571	0	0
T135	3055	0	0	0
T140	759	0	0	0
T173	2858	0	0	0
T213	1816	0	0	0
T231	346052	4149	0	0
T232	205483	0	0	0
T233	0	12581	0	0
T234	0	1518	0	0
T235	0	3616	0	0
T236	0	7818	0	0
T237	0	3239	0	0
T238	0	1871	0	0
T239	0	5442	0	0
T240	0	7156	0	0
T241	0	2538	0	0
T242	1713	0	0	0
T243	1872	0	0	0
T244	3071	0	0	0
T245	7058	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238904474	66775	0	0
T5	1949	0	0	0
T22	1860	0	0	0
T23	3949	0	0	0
T41	597	0	0	0
T46	1960	0	0	0
T51	2543	0	0	0
T85	10052	114	0	0
T86	1470	0	0	0
T87	2774	0	0	0
T90	874	0	0	0
T113	0	41	0	0
T231	0	4012	0	0
T233	0	11448	0	0
T234	0	1875	0	0
T235	0	3220	0	0
T247	0	86	0	0
T253	0	69	0	0
T254	0	29	0	0
T255	0	34	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238904474	62060	0	0
T135	3055	0	0	0
T140	759	0	0	0
T173	2858	0	0	0
T213	1816	0	0	0
T231	346052	3615	0	0
T232	205483	0	0	0
T233	0	10733	0	0
T234	0	1614	0	0
T235	0	3373	0	0
T236	0	7136	0	0
T237	0	2961	0	0
T238	0	1678	0	0
T239	0	4620	0	0
T240	0	5724	0	0
T241	0	2194	0	0
T242	1713	0	0	0
T243	1872	0	0	0
T244	3071	0	0	0
T245	7058	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238904474	71176	0	0
T135	3055	0	0	0
T140	759	0	0	0
T173	2858	0	0	0
T213	1816	0	0	0
T231	346052	4148	0	0
T232	205483	0	0	0
T233	0	12585	0	0
T234	0	1711	0	0
T235	0	3964	0	0
T236	0	8177	0	0
T237	0	3119	0	0
T238	0	2139	0	0
T239	0	5270	0	0
T240	0	7167	0	0
T241	0	2412	0	0
T242	1713	0	0	0
T243	1872	0	0	0
T244	3071	0	0	0
T245	7058	0	0	0