EDN Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: `fdfa12db04`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.070s	18.370us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.970s	18.239us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.000s	16.319us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.640s	1.835ms	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.570s	38.393us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.900s	46.611us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.000s	16.319us	20	20	100.00
		edn_csr_aliasing	1.570s	38.393us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	4.960s	620.239us	300	300	100.00
V2	csrng_commands	edn_genbits	4.960s	620.239us	300	300	100.00
V2	genbits	edn_genbits	4.960s	620.239us	300	300	100.00
V2	interrupts	edn_intr	1.290s	38.079us	50	50	100.00
V2	alerts	edn_alert	1.530s	280.450us	200	200	100.00
V2	errs	edn_err	1.570s	37.599us	100	100	100.00
V2	disable	edn_disable	1.010s	14.671us	50	50	100.00
		edn_disable_auto_req_mode	1.430s	47.609us	50	50	100.00
V2	stress_all	edn_stress_all	6.700s	432.127us	50	50	100.00
V2	intr_test	edn_intr_test	1.040s	104.873us	50	50	100.00
V2	alert_test	edn_alert_test	1.110s	60.649us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.840s	1.949ms	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.840s	1.949ms	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.970s	18.239us	5	5	100.00
		edn_csr_rw	1.000s	16.319us	20	20	100.00
		edn_csr_aliasing	1.570s	38.393us	5	5	100.00
		edn_same_csr_outstanding	1.540s	154.770us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.970s	18.239us	5	5	100.00
		edn_csr_rw	1.000s	16.319us	20	20	100.00
		edn_csr_aliasing	1.570s	38.393us	5	5	100.00
		edn_same_csr_outstanding	1.540s	154.770us	20	20	100.00
V2		TOTAL			940	940	100.00
V2S	tl_intg_err	edn_sec_cm	0.900s	14.007us	0	5	0.00
		edn_tl_intg_err	2.820s	97.910us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.050s	52.148us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.530s	280.450us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	0.900s	14.007us	0	5	0.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	0.900s	14.007us	0	5	0.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	0.900s	14.007us	0	5	0.00
V2S	sec_cm_ctr_redun	edn_sec_cm	0.900s	14.007us	0	5	0.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.530s	280.450us	200	200	100.00
		edn_sec_cm	0.900s	14.007us	0	5	0.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.530s	280.450us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.820s	97.910us	20	20	100.00
V2S		TOTAL			30	35	85.71
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	36.489m	389.104ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1125	1130	99.56

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	3	3	2	66.67
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.38	98.25	93.25	91.10	86.63	95.50	96.83	92.08

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: edn_reg_block.main_sm_state reset value: *

has 5 failures:

Test edn_sec_cm has 5 failures.

0.edn_sec_cm.107933816320044047908866759622914514438018341679845200360836178332260983259580
Line 274, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_sec_cm/latest/run.log

  UVM_ERROR @   7498513 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (193 [0xc1] vs 382 [0x17e]) Regname: edn_reg_block.main_sm_state reset value: 0xc1
  UVM_INFO @   7498513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.edn_sec_cm.20393957514647825981167889705000703067412640225545641982970820917715422997187
Line 270, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_sec_cm/latest/run.log

  UVM_ERROR @  14007346 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (193 [0xc1] vs 382 [0x17e]) Regname: edn_reg_block.main_sm_state reset value: 0xc1
  UVM_INFO @  14007346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.