EDN Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: `4877b481e8`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.060s	17.393us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.000s	21.854us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.960s	23.174us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.400s	186.557us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.730s	159.606us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.860s	49.871us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.960s	23.174us	20	20	100.00
		edn_csr_aliasing	1.730s	159.606us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	2.367m	12.165ms	300	300	100.00
V2	csrng_commands	edn_genbits	2.367m	12.165ms	300	300	100.00
V2	genbits	edn_genbits	2.367m	12.165ms	300	300	100.00
V2	interrupts	edn_intr	1.230s	31.234us	50	50	100.00
V2	alerts	edn_alert	1.490s	31.797us	200	200	100.00
V2	errs	edn_err	1.490s	33.972us	100	100	100.00
V2	disable	edn_disable	0.970s	12.462us	50	50	100.00
		edn_disable_auto_req_mode	1.520s	77.803us	50	50	100.00
V2	stress_all	edn_stress_all	7.740s	405.780us	50	50	100.00
V2	intr_test	edn_intr_test	1.000s	14.740us	50	50	100.00
V2	alert_test	edn_alert_test	1.180s	57.897us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	5.270s	172.707us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	5.270s	172.707us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.000s	21.854us	5	5	100.00
		edn_csr_rw	0.960s	23.174us	20	20	100.00
		edn_csr_aliasing	1.730s	159.606us	5	5	100.00
		edn_same_csr_outstanding	1.500s	259.762us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.000s	21.854us	5	5	100.00
		edn_csr_rw	0.960s	23.174us	20	20	100.00
		edn_csr_aliasing	1.730s	159.606us	5	5	100.00
		edn_same_csr_outstanding	1.500s	259.762us	20	20	100.00
V2		TOTAL			940	940	100.00
V2S	tl_intg_err	edn_sec_cm	1.120s	22.574us	0	5	0.00
		edn_tl_intg_err	3.630s	159.392us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.010s	31.091us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.490s	31.797us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	1.120s	22.574us	0	5	0.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	1.120s	22.574us	0	5	0.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	1.120s	22.574us	0	5	0.00
V2S	sec_cm_ctr_redun	edn_sec_cm	1.120s	22.574us	0	5	0.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.490s	31.797us	200	200	100.00
		edn_sec_cm	1.120s	22.574us	0	5	0.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.490s	31.797us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.630s	159.392us	20	20	100.00
V2S		TOTAL			30	35	85.71
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	55.059m	539.762ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1125	1130	99.56

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	3	3	2	66.67
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.71	98.25	93.31	90.85	89.53	95.50	96.83	91.70

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: edn_reg_block.main_sm_state reset value: *

has 5 failures:

Test edn_sec_cm has 5 failures.

0.edn_sec_cm.55325760359360200189628578188198229318382723640460909059626101433592808530987
Line 268, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_sec_cm/latest/run.log

  UVM_ERROR @  24762679 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (149 [0x95] vs 382 [0x17e]) Regname: edn_reg_block.main_sm_state reset value: 0xc1
  UVM_INFO @  24762679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.edn_sec_cm.106341967242864388227797109788711091650149884755277301578512132309957702403004
Line 265, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_sec_cm/latest/run.log

  UVM_ERROR @   3013475 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (193 [0xc1] vs 382 [0x17e]) Regname: edn_reg_block.main_sm_state reset value: 0xc1
  UVM_INFO @   3013475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.