EDN Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: e439226b6c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.080s 17.439us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.230s 39.831us 5 5 100.00
V1 csr_rw edn_csr_rw 1.120s 36.635us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.640s 672.844us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.450s 50.894us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.010s 76.537us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.120s 36.635us 20 20 100.00
edn_csr_aliasing 1.450s 50.894us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 4.250s 511.751us 300 300 100.00
V2 csrng_commands edn_genbits 4.250s 511.751us 300 300 100.00
V2 genbits edn_genbits 4.250s 511.751us 300 300 100.00
V2 interrupts edn_intr 1.260s 21.562us 50 50 100.00
V2 alerts edn_alert 1.550s 35.243us 200 200 100.00
V2 errs edn_err 1.330s 138.991us 100 100 100.00
V2 disable edn_disable 8.140s 500.000us 49 50 98.00
edn_disable_auto_req_mode 1.650s 50.378us 50 50 100.00
V2 stress_all edn_stress_all 8.050s 451.103us 50 50 100.00
V2 intr_test edn_intr_test 1.010s 14.843us 50 50 100.00
V2 alert_test edn_alert_test 1.410s 179.348us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.410s 248.823us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.410s 248.823us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.230s 39.831us 5 5 100.00
edn_csr_rw 1.120s 36.635us 20 20 100.00
edn_csr_aliasing 1.450s 50.894us 5 5 100.00
edn_same_csr_outstanding 1.530s 365.121us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.230s 39.831us 5 5 100.00
edn_csr_rw 1.120s 36.635us 20 20 100.00
edn_csr_aliasing 1.450s 50.894us 5 5 100.00
edn_same_csr_outstanding 1.530s 365.121us 20 20 100.00
V2 TOTAL 939 940 99.89
V2S tl_intg_err edn_sec_cm 9.160s 2.194ms 5 5 100.00
edn_tl_intg_err 5.240s 302.594us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.090s 16.197us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.550s 35.243us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 9.160s 2.194ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 9.160s 2.194ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 9.160s 2.194ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 9.160s 2.194ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.550s 35.243us 200 200 100.00
edn_sec_cm 9.160s 2.194ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.550s 35.243us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 5.240s 302.594us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 46.029m 506.721ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1129 1130 99.91

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 10 90.91
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.56 98.25 93.91 97.07 91.28 96.37 99.77 92.28

Failure Buckets

Past Results