EDN Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: `625f353e9c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.070s	20.159us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.980s	29.735us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.940s	12.276us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.570s	267.130us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.480s	135.571us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.970s	54.551us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.940s	12.276us	20	20	100.00
		edn_csr_aliasing	1.480s	135.571us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.234m	2.223ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.234m	2.223ms	300	300	100.00
V2	genbits	edn_genbits	1.234m	2.223ms	300	300	100.00
V2	interrupts	edn_intr	1.220s	22.975us	50	50	100.00
V2	alerts	edn_alert	1.590s	159.562us	200	200	100.00
V2	errs	edn_err	1.330s	30.641us	100	100	100.00
V2	disable	edn_disable	0.950s	14.758us	50	50	100.00
		edn_disable_auto_req_mode	1.430s	48.481us	50	50	100.00
V2	stress_all	edn_stress_all	6.880s	473.725us	50	50	100.00
V2	intr_test	edn_intr_test	1.030s	17.291us	50	50	100.00
V2	alert_test	edn_alert_test	1.410s	94.284us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.490s	2.458ms	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.490s	2.458ms	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.980s	29.735us	5	5	100.00
		edn_csr_rw	0.940s	12.276us	20	20	100.00
		edn_csr_aliasing	1.480s	135.571us	5	5	100.00
		edn_same_csr_outstanding	1.510s	37.408us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.980s	29.735us	5	5	100.00
		edn_csr_rw	0.940s	12.276us	20	20	100.00
		edn_csr_aliasing	1.480s	135.571us	5	5	100.00
		edn_same_csr_outstanding	1.510s	37.408us	20	20	100.00
V2		TOTAL			940	940	100.00
V2S	tl_intg_err	edn_sec_cm	1.540s	264.083us	0	5	0.00
		edn_tl_intg_err	5.070s	273.965us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.080s	19.850us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.590s	159.562us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	1.540s	264.083us	0	5	0.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	1.540s	264.083us	0	5	0.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	1.540s	264.083us	0	5	0.00
V2S	sec_cm_ctr_redun	edn_sec_cm	1.540s	264.083us	0	5	0.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.590s	159.562us	200	200	100.00
		edn_sec_cm	1.540s	264.083us	0	5	0.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.590s	159.562us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	5.070s	273.965us	20	20	100.00
V2S		TOTAL			30	35	85.71
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	50.977m	175.210ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1125	1130	99.56

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	3	3	2	66.67
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.41	98.25	93.31	91.10	87.21	95.50	96.83	91.70

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: edn_reg_block.main_sm_state reset value: *

has 5 failures:

Test edn_sec_cm has 5 failures.

0.edn_sec_cm.103076741689043119030894071501606091183695737724110540208421064691996655640827
Line 267, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_sec_cm/latest/run.log

  UVM_ERROR @  80590131 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (193 [0xc1] vs 382 [0x17e]) Regname: edn_reg_block.main_sm_state reset value: 0xc1
  UVM_INFO @  80590131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.edn_sec_cm.46609064618485772037067965119295699425277487147130294792993985614524552179412
Line 272, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_sec_cm/latest/run.log

  UVM_ERROR @  11305990 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (193 [0xc1] vs 382 [0x17e]) Regname: edn_reg_block.main_sm_state reset value: 0xc1
  UVM_INFO @  11305990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.