EDN Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.110s	19.288us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.040s	33.515us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.030s	19.194us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.530s	131.929us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.250s	51.384us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.140s	93.289us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.030s	19.194us	20	20	100.00
		edn_csr_aliasing	1.250s	51.384us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	4.090s	506.957us	300	300	100.00
V2	csrng_commands	edn_genbits	4.090s	506.957us	300	300	100.00
V2	genbits	edn_genbits	4.090s	506.957us	300	300	100.00
V2	interrupts	edn_intr	1.290s	22.442us	50	50	100.00
V2	alerts	edn_alert	1.420s	159.857us	200	200	100.00
V2	errs	edn_err	1.390s	29.304us	100	100	100.00
V2	disable	edn_disable	1.020s	57.126us	50	50	100.00
		edn_disable_auto_req_mode	1.490s	47.913us	50	50	100.00
V2	stress_all	edn_stress_all	8.310s	429.358us	50	50	100.00
V2	intr_test	edn_intr_test	1.000s	124.442us	50	50	100.00
V2	alert_test	edn_alert_test	1.390s	78.589us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.660s	253.431us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.660s	253.431us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.040s	33.515us	5	5	100.00
		edn_csr_rw	1.030s	19.194us	20	20	100.00
		edn_csr_aliasing	1.250s	51.384us	5	5	100.00
		edn_same_csr_outstanding	1.410s	108.265us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.040s	33.515us	5	5	100.00
		edn_csr_rw	1.030s	19.194us	20	20	100.00
		edn_csr_aliasing	1.250s	51.384us	5	5	100.00
		edn_same_csr_outstanding	1.410s	108.265us	20	20	100.00
V2		TOTAL			940	940	100.00
V2S	tl_intg_err	edn_sec_cm	2.480s	210.945us	0	5	0.00
		edn_tl_intg_err	3.560s	164.503us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.080s	17.462us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.420s	159.857us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	2.480s	210.945us	0	5	0.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	2.480s	210.945us	0	5	0.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	2.480s	210.945us	0	5	0.00
V2S	sec_cm_ctr_redun	edn_sec_cm	2.480s	210.945us	0	5	0.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.420s	159.857us	200	200	100.00
		edn_sec_cm	2.480s	210.945us	0	5	0.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.420s	159.857us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.560s	164.503us	20	20	100.00
V2S		TOTAL			30	35	85.71
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	43.399m	407.698ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1124	1130	99.47

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	3	3	2	66.67
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.51	98.25	93.25	91.05	87.79	95.50	96.83	91.89

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: edn_reg_block.main_sm_state reset value: *

has 5 failures:

Test edn_sec_cm has 5 failures.

0.edn_sec_cm.77916333952812649637019188102328425568050961155833662513977976066025038879323
Line 453, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_sec_cm/latest/run.log

  UVM_ERROR @ 210944819 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (193 [0xc1] vs 382 [0x17e]) Regname: edn_reg_block.main_sm_state reset value: 0xc1
  UVM_INFO @ 210944819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.edn_sec_cm.39594199287502884996313759294261243136265327566948308029784615093619490127521
Line 271, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_sec_cm/latest/run.log

  UVM_ERROR @  27421821 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (149 [0x95] vs 382 [0x17e]) Regname: edn_reg_block.main_sm_state reset value: 0xc1
  UVM_INFO @  27421821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:755) [edn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test edn_stress_all_with_rand_reset has 1 failures.
  - 31.edn_stress_all_with_rand_reset.57570755904215892713376902986766247439992341928987781727670885564858100462972
    Line 857, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/31.edn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 37044438611 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 37044438611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```