Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 94.44 83.33 100.00 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.11 98.25 93.97 97.02 91.28 96.37 99.77


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
edn_csr_assert 100.00 100.00
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_edn_core 94.03 99.92 92.75 82.54 91.28 98.83 98.88
u_edn_cov_if 25.00 50.00 0.00
u_reg 96.95 95.02 97.57 100.00 92.16 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Cond Coverage for Module : edn
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T20,T8

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T13,T14
10CoveredT3,T4,T5

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 69 69 100.00
Total Bits 1172 1172 100.00
Total Bits 0->1 586 586 100.00
Total Bits 1->0 586 586 100.00

Ports 69 69 100.00
Port Bits 1172 1172 100.00
Port Bits 0->1 586 586 100.00
Port Bits 1->0 586 586 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T2,T20,T8 Yes T2,T19,T20 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T2,T3,T5 Yes T2,T3,T5 INPUT
edn_i[1].edn_req Yes Yes T2,T5,T8 Yes T2,T5,T8 INPUT
edn_i[2].edn_req Yes Yes T2,T5,T20 Yes T2,T5,T20 INPUT
edn_i[3].edn_req Yes Yes T2,T5,T8 Yes T2,T5,T8 INPUT
edn_i[4].edn_req Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT
edn_i[5].edn_req Yes Yes T2,T5,T30 Yes T2,T5,T30 INPUT
edn_i[6].edn_req Yes Yes T2,T4,T5 Yes T2,T4,T5 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T2,T3,T31 Yes T2,T3,T31 OUTPUT
edn_o[0].edn_fips Yes Yes T2,T6,T31 Yes T2,T6,T31 OUTPUT
edn_o[0].edn_ack Yes Yes T2,T3,T6 Yes T2,T3,T6 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T30,T32,T33 Yes T2,T30,T32 OUTPUT
edn_o[1].edn_fips Yes Yes T30,T34,T35 Yes T2,T8,T30 OUTPUT
edn_o[1].edn_ack Yes Yes T2,T8,T30 Yes T2,T8,T30 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T2,T20,T30 Yes T2,T20,T30 OUTPUT
edn_o[2].edn_fips Yes Yes T30,T36,T10 Yes T2,T20,T30 OUTPUT
edn_o[2].edn_ack Yes Yes T2,T20,T30 Yes T2,T20,T30 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T2,T8,T30 Yes T2,T8,T30 OUTPUT
edn_o[3].edn_fips Yes Yes T30,T17,T37 Yes T2,T30,T33 OUTPUT
edn_o[3].edn_ack Yes Yes T2,T8,T30 Yes T2,T8,T30 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T1,T2,T19 Yes T1,T2,T19 OUTPUT
edn_o[4].edn_fips Yes Yes T30,T33,T38 Yes T30,T33,T17 OUTPUT
edn_o[4].edn_ack Yes Yes T1,T2,T19 Yes T1,T2,T19 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T2,T30,T39 Yes T2,T30,T39 OUTPUT
edn_o[5].edn_fips Yes Yes T2,T30,T7 Yes T2,T30,T7 OUTPUT
edn_o[5].edn_ack Yes Yes T2,T30,T39 Yes T2,T30,T39 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T2,T30,T40 Yes T2,T30,T40 OUTPUT
edn_o[6].edn_fips Yes Yes T30,T10,T41 Yes T2,T30,T42 OUTPUT
edn_o[6].edn_ack Yes Yes T2,T30,T40 Yes T2,T30,T40 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T2,T43,T30 Yes T2,T31,T30 INPUT
csrng_cmd_i.genbits_fips Yes Yes T2,T31,T30 Yes T2,T8,T43 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] Yes Yes T1,T20,T8 Yes T1,T20,T8 INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T1,T20,T8 Yes T1,T20,T8 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T1,T20,T8 Yes T1,T20,T8 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T44,T45,T21 Yes T44,T45,T21 OUTPUT
intr_edn_fatal_err_o Yes Yes T3,T44,T46 Yes T3,T44,T46 OUTPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : edn
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 47 47 100.00 47 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 47 47 100.00 47 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertTxKnownO_A 11097801 10897742 0 0
CsrngAppIfOut_A 11097801 10897742 0 0
FpvSecCmCntAlertCheck_A 11097801 127 0 0
FpvSecCmGenCmdFifoRptrCheck_A 11097801 90 0 0
FpvSecCmGenCmdFifoWptrCheck_A 11097801 90 0 0
FpvSecCmMainFsmCheck_A 11097801 90 0 0
FpvSecCmRegWeOnehotCheck_A 11097801 90 0 0
FpvSecCmResCmdFifoRptrCheck_A 11097801 90 0 0
FpvSecCmResCmdFifoWptrCheck_A 11097801 90 0 0
IntrEdnCmdReqDoneKnownO_A 11097801 10897742 0 0
TlAReadyKnownO_A 11097801 10897742 0 0
TlDValidKnownO_A 11097801 10897742 0 0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A 11097801 90 0 0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A 11097801 90 0 0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A 11097801 90 0 0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A 11097801 90 0 0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A 11097801 90 0 0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A 11097801 90 0 0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A 11097801 90 0 0
gen_edn_if_asserts[0].EdnDataStableDisable_A 11097801 572226 0 280
gen_edn_if_asserts[0].EdnDataStable_A 11097801 20987 0 413
gen_edn_if_asserts[0].EdnEndPointOut_A 11097801 10897742 0 0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A 11097801 154982 0 0
gen_edn_if_asserts[1].EdnDataStableDisable_A 11097801 572226 0 280
gen_edn_if_asserts[1].EdnDataStable_A 11097801 3711 0 133
gen_edn_if_asserts[1].EdnEndPointOut_A 11097801 10897742 0 0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A 11097801 154982 0 0
gen_edn_if_asserts[2].EdnDataStableDisable_A 11097801 572226 0 280
gen_edn_if_asserts[2].EdnDataStable_A 11097801 3918 0 122
gen_edn_if_asserts[2].EdnEndPointOut_A 11097801 10897742 0 0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A 11097801 154982 0 0
gen_edn_if_asserts[3].EdnDataStableDisable_A 11097801 572226 0 280
gen_edn_if_asserts[3].EdnDataStable_A 11097801 4510 0 103
gen_edn_if_asserts[3].EdnEndPointOut_A 11097801 10897742 0 0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A 11097801 154982 0 0
gen_edn_if_asserts[4].EdnDataStableDisable_A 11097801 572226 0 280
gen_edn_if_asserts[4].EdnDataStable_A 11097801 1425 0 96
gen_edn_if_asserts[4].EdnEndPointOut_A 11097801 10897742 0 0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A 11097801 154982 0 0
gen_edn_if_asserts[5].EdnDataStableDisable_A 11097801 572226 0 280
gen_edn_if_asserts[5].EdnDataStable_A 11097801 2374 0 99
gen_edn_if_asserts[5].EdnEndPointOut_A 11097801 10897742 0 0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A 11097801 154982 0 0
gen_edn_if_asserts[6].EdnDataStableDisable_A 11097801 572226 0 280
gen_edn_if_asserts[6].EdnDataStable_A 11097801 2201 0 86
gen_edn_if_asserts[6].EdnEndPointOut_A 11097801 10897742 0 0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A 11097801 154982 0 0


AlertTxKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 10897742 0 0
T1 2889 2836 0 0
T2 1812 1715 0 0
T3 1166 990 0 0
T4 2186 2068 0 0
T5 42906 21480 0 0
T6 817 674 0 0
T8 3085 3035 0 0
T9 1444 1376 0 0
T19 1073 1018 0 0
T20 2395 2323 0 0

CsrngAppIfOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 10897742 0 0
T1 2889 2836 0 0
T2 1812 1715 0 0
T3 1166 990 0 0
T4 2186 2068 0 0
T5 42906 21480 0 0
T6 817 674 0 0
T8 3085 3035 0 0
T9 1444 1376 0 0
T19 1073 1018 0 0
T20 2395 2323 0 0

FpvSecCmCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 127 0 0
T4 2186 1 0 0
T5 42906 20 0 0
T6 817 1 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T13 0 20 0 0
T19 1073 0 0 0
T20 2395 0 0 0
T31 2401 0 0 0
T43 1628 0 0 0
T47 0 1 0 0
T48 0 1 0 0
T49 0 1 0 0
T50 0 1 0 0
T51 0 1 0 0
T52 0 1 0 0
T53 935 0 0 0

FpvSecCmGenCmdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 90 0 0
T5 42906 20 0 0
T6 817 0 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T13 0 20 0 0
T14 0 20 0 0
T19 1073 0 0 0
T20 2395 0 0 0
T30 4892 0 0 0
T31 2401 0 0 0
T43 1628 0 0 0
T53 935 0 0 0
T54 0 20 0 0
T55 0 10 0 0

FpvSecCmGenCmdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 90 0 0
T5 42906 20 0 0
T6 817 0 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T13 0 20 0 0
T14 0 20 0 0
T19 1073 0 0 0
T20 2395 0 0 0
T30 4892 0 0 0
T31 2401 0 0 0
T43 1628 0 0 0
T53 935 0 0 0
T54 0 20 0 0
T55 0 10 0 0

FpvSecCmMainFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 90 0 0
T5 42906 20 0 0
T6 817 0 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T13 0 20 0 0
T14 0 20 0 0
T19 1073 0 0 0
T20 2395 0 0 0
T30 4892 0 0 0
T31 2401 0 0 0
T43 1628 0 0 0
T53 935 0 0 0
T54 0 20 0 0
T55 0 10 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 90 0 0
T5 42906 20 0 0
T6 817 0 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T13 0 20 0 0
T14 0 20 0 0
T19 1073 0 0 0
T20 2395 0 0 0
T30 4892 0 0 0
T31 2401 0 0 0
T43 1628 0 0 0
T53 935 0 0 0
T54 0 20 0 0
T55 0 10 0 0

FpvSecCmResCmdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 90 0 0
T5 42906 20 0 0
T6 817 0 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T13 0 20 0 0
T14 0 20 0 0
T19 1073 0 0 0
T20 2395 0 0 0
T30 4892 0 0 0
T31 2401 0 0 0
T43 1628 0 0 0
T53 935 0 0 0
T54 0 20 0 0
T55 0 10 0 0

FpvSecCmResCmdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 90 0 0
T5 42906 20 0 0
T6 817 0 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T13 0 20 0 0
T14 0 20 0 0
T19 1073 0 0 0
T20 2395 0 0 0
T30 4892 0 0 0
T31 2401 0 0 0
T43 1628 0 0 0
T53 935 0 0 0
T54 0 20 0 0
T55 0 10 0 0

IntrEdnCmdReqDoneKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 10897742 0 0
T1 2889 2836 0 0
T2 1812 1715 0 0
T3 1166 990 0 0
T4 2186 2068 0 0
T5 42906 21480 0 0
T6 817 674 0 0
T8 3085 3035 0 0
T9 1444 1376 0 0
T19 1073 1018 0 0
T20 2395 2323 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 10897742 0 0
T1 2889 2836 0 0
T2 1812 1715 0 0
T3 1166 990 0 0
T4 2186 2068 0 0
T5 42906 21480 0 0
T6 817 674 0 0
T8 3085 3035 0 0
T9 1444 1376 0 0
T19 1073 1018 0 0
T20 2395 2323 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 10897742 0 0
T1 2889 2836 0 0
T2 1812 1715 0 0
T3 1166 990 0 0
T4 2186 2068 0 0
T5 42906 21480 0 0
T6 817 674 0 0
T8 3085 3035 0 0
T9 1444 1376 0 0
T19 1073 1018 0 0
T20 2395 2323 0 0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 90 0 0
T5 42906 20 0 0
T6 817 0 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T13 0 20 0 0
T14 0 20 0 0
T19 1073 0 0 0
T20 2395 0 0 0
T30 4892 0 0 0
T31 2401 0 0 0
T43 1628 0 0 0
T53 935 0 0 0
T54 0 20 0 0
T55 0 10 0 0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 90 0 0
T5 42906 20 0 0
T6 817 0 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T13 0 20 0 0
T14 0 20 0 0
T19 1073 0 0 0
T20 2395 0 0 0
T30 4892 0 0 0
T31 2401 0 0 0
T43 1628 0 0 0
T53 935 0 0 0
T54 0 20 0 0
T55 0 10 0 0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 90 0 0
T5 42906 20 0 0
T6 817 0 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T13 0 20 0 0
T14 0 20 0 0
T19 1073 0 0 0
T20 2395 0 0 0
T30 4892 0 0 0
T31 2401 0 0 0
T43 1628 0 0 0
T53 935 0 0 0
T54 0 20 0 0
T55 0 10 0 0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 90 0 0
T5 42906 20 0 0
T6 817 0 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T13 0 20 0 0
T14 0 20 0 0
T19 1073 0 0 0
T20 2395 0 0 0
T30 4892 0 0 0
T31 2401 0 0 0
T43 1628 0 0 0
T53 935 0 0 0
T54 0 20 0 0
T55 0 10 0 0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 90 0 0
T5 42906 20 0 0
T6 817 0 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T13 0 20 0 0
T14 0 20 0 0
T19 1073 0 0 0
T20 2395 0 0 0
T30 4892 0 0 0
T31 2401 0 0 0
T43 1628 0 0 0
T53 935 0 0 0
T54 0 20 0 0
T55 0 10 0 0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 90 0 0
T5 42906 20 0 0
T6 817 0 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T13 0 20 0 0
T14 0 20 0 0
T19 1073 0 0 0
T20 2395 0 0 0
T30 4892 0 0 0
T31 2401 0 0 0
T43 1628 0 0 0
T53 935 0 0 0
T54 0 20 0 0
T55 0 10 0 0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 90 0 0
T5 42906 20 0 0
T6 817 0 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T13 0 20 0 0
T14 0 20 0 0
T19 1073 0 0 0
T20 2395 0 0 0
T30 4892 0 0 0
T31 2401 0 0 0
T43 1628 0 0 0
T53 935 0 0 0
T54 0 20 0 0
T55 0 10 0 0

gen_edn_if_asserts[0].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 572226 0 280
T1 2889 548 0 0
T2 1812 12 0 0
T3 1166 512 0 0
T4 2186 1448 0 0
T5 42906 16063 0 2
T6 817 363 0 0
T8 3085 395 0 0
T9 1444 134 0 0
T13 0 0 0 2
T19 1073 73 0 0
T20 2395 343 0 0
T27 0 0 0 2
T28 0 0 0 2
T29 0 0 0 2
T56 0 0 0 2
T57 0 0 0 2
T58 0 0 0 2
T59 0 0 0 2
T60 0 0 0 2

gen_edn_if_asserts[0].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 20987 0 413
T2 1812 22 0 1
T3 1166 1 0 0
T4 2186 0 0 0
T5 42906 0 0 0
T6 817 1 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T19 1073 0 0 0
T20 2395 0 0 0
T30 0 12 0 1
T31 2401 15 0 1
T43 0 15 0 1
T44 0 12 0 0
T53 0 3 0 1
T61 0 15 0 1
T62 0 3 0 1
T63 0 0 0 1
T64 0 0 0 1
T65 0 0 0 1

gen_edn_if_asserts[0].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 10897742 0 0
T1 2889 2836 0 0
T2 1812 1715 0 0
T3 1166 990 0 0
T4 2186 2068 0 0
T5 42906 21480 0 0
T6 817 674 0 0
T8 3085 3035 0 0
T9 1444 1376 0 0
T19 1073 1018 0 0
T20 2395 2323 0 0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 154982 0 0
T3 1166 7 0 0
T4 2186 1093 0 0
T5 42906 14635 0 0
T6 817 324 0 0
T7 0 328 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T13 0 22074 0 0
T18 0 718 0 0
T19 1073 0 0 0
T20 2395 0 0 0
T31 2401 0 0 0
T43 1628 0 0 0
T46 0 1101 0 0
T66 0 1102 0 0
T67 0 362 0 0

gen_edn_if_asserts[1].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 572226 0 280
T1 2889 548 0 0
T2 1812 12 0 0
T3 1166 512 0 0
T4 2186 1448 0 0
T5 42906 16063 0 2
T6 817 363 0 0
T8 3085 395 0 0
T9 1444 134 0 0
T13 0 0 0 2
T19 1073 73 0 0
T20 2395 343 0 0
T27 0 0 0 2
T28 0 0 0 2
T29 0 0 0 2
T56 0 0 0 2
T57 0 0 0 2
T58 0 0 0 2
T59 0 0 0 2
T60 0 0 0 2

gen_edn_if_asserts[1].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 3711 0 133
T2 1812 3 0 1
T3 1166 0 0 0
T4 2186 0 0 0
T5 42906 0 0 0
T6 817 0 0 0
T8 3085 4 0 1
T9 1444 0 0 0
T10 0 3 0 1
T19 1073 0 0 0
T20 2395 0 0 0
T30 0 50 0 1
T31 2401 0 0 0
T32 0 3 0 1
T33 0 3 0 1
T34 0 38 0 1
T35 0 43 0 1
T37 0 3 0 1
T38 0 3 0 1

gen_edn_if_asserts[1].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 10897742 0 0
T1 2889 2836 0 0
T2 1812 1715 0 0
T3 1166 990 0 0
T4 2186 2068 0 0
T5 42906 21480 0 0
T6 817 674 0 0
T8 3085 3035 0 0
T9 1444 1376 0 0
T19 1073 1018 0 0
T20 2395 2323 0 0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 154982 0 0
T3 1166 7 0 0
T4 2186 1093 0 0
T5 42906 14635 0 0
T6 817 324 0 0
T7 0 328 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T13 0 22074 0 0
T18 0 718 0 0
T19 1073 0 0 0
T20 2395 0 0 0
T31 2401 0 0 0
T43 1628 0 0 0
T46 0 1101 0 0
T66 0 1102 0 0
T67 0 362 0 0

gen_edn_if_asserts[2].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 572226 0 280
T1 2889 548 0 0
T2 1812 12 0 0
T3 1166 512 0 0
T4 2186 1448 0 0
T5 42906 16063 0 2
T6 817 363 0 0
T8 3085 395 0 0
T9 1444 134 0 0
T13 0 0 0 2
T19 1073 73 0 0
T20 2395 343 0 0
T27 0 0 0 2
T28 0 0 0 2
T29 0 0 0 2
T56 0 0 0 2
T57 0 0 0 2
T58 0 0 0 2
T59 0 0 0 2
T60 0 0 0 2

gen_edn_if_asserts[2].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 3918 0 122
T2 1812 3 0 1
T3 1166 0 0 0
T4 2186 0 0 0
T5 42906 0 0 0
T6 817 0 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T10 0 6 0 1
T19 1073 0 0 0
T20 2395 4 0 1
T30 0 46 0 1
T31 2401 0 0 0
T33 0 5 0 1
T35 0 0 0 1
T36 0 4 0 0
T38 0 0 0 1
T40 0 4 0 0
T46 0 1 0 0
T68 0 3 0 1
T69 0 3 0 1
T70 0 0 0 1

gen_edn_if_asserts[2].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 10897742 0 0
T1 2889 2836 0 0
T2 1812 1715 0 0
T3 1166 990 0 0
T4 2186 2068 0 0
T5 42906 21480 0 0
T6 817 674 0 0
T8 3085 3035 0 0
T9 1444 1376 0 0
T19 1073 1018 0 0
T20 2395 2323 0 0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 154982 0 0
T3 1166 7 0 0
T4 2186 1093 0 0
T5 42906 14635 0 0
T6 817 324 0 0
T7 0 328 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T13 0 22074 0 0
T18 0 718 0 0
T19 1073 0 0 0
T20 2395 0 0 0
T31 2401 0 0 0
T43 1628 0 0 0
T46 0 1101 0 0
T66 0 1102 0 0
T67 0 362 0 0

gen_edn_if_asserts[3].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 572226 0 280
T1 2889 548 0 0
T2 1812 12 0 0
T3 1166 512 0 0
T4 2186 1448 0 0
T5 42906 16063 0 2
T6 817 363 0 0
T8 3085 395 0 0
T9 1444 134 0 0
T13 0 0 0 2
T19 1073 73 0 0
T20 2395 343 0 0
T27 0 0 0 2
T28 0 0 0 2
T29 0 0 0 2
T56 0 0 0 2
T57 0 0 0 2
T58 0 0 0 2
T59 0 0 0 2
T60 0 0 0 2

gen_edn_if_asserts[3].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 4510 0 103
T2 1812 3 0 1
T3 1166 0 0 0
T4 2186 0 0 0
T5 42906 0 0 0
T6 817 0 0 0
T8 3085 4 0 0
T9 1444 0 0 0
T10 0 3 0 1
T17 0 32 0 1
T19 1073 0 0 0
T20 2395 0 0 0
T30 0 49 0 1
T31 2401 0 0 0
T33 0 3 0 1
T35 0 934 0 1
T37 0 43 0 1
T38 0 12 0 1
T71 0 4 0 1
T72 0 0 0 1

gen_edn_if_asserts[3].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 10897742 0 0
T1 2889 2836 0 0
T2 1812 1715 0 0
T3 1166 990 0 0
T4 2186 2068 0 0
T5 42906 21480 0 0
T6 817 674 0 0
T8 3085 3035 0 0
T9 1444 1376 0 0
T19 1073 1018 0 0
T20 2395 2323 0 0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 154982 0 0
T3 1166 7 0 0
T4 2186 1093 0 0
T5 42906 14635 0 0
T6 817 324 0 0
T7 0 328 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T13 0 22074 0 0
T18 0 718 0 0
T19 1073 0 0 0
T20 2395 0 0 0
T31 2401 0 0 0
T43 1628 0 0 0
T46 0 1101 0 0
T66 0 1102 0 0
T67 0 362 0 0

gen_edn_if_asserts[4].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 572226 0 280
T1 2889 548 0 0
T2 1812 12 0 0
T3 1166 512 0 0
T4 2186 1448 0 0
T5 42906 16063 0 2
T6 817 363 0 0
T8 3085 395 0 0
T9 1444 134 0 0
T13 0 0 0 2
T19 1073 73 0 0
T20 2395 343 0 0
T27 0 0 0 2
T28 0 0 0 2
T29 0 0 0 2
T56 0 0 0 2
T57 0 0 0 2
T58 0 0 0 2
T59 0 0 0 2
T60 0 0 0 2

gen_edn_if_asserts[4].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 1425 0 96
T1 2889 4 0 1
T2 1812 3 0 1
T3 1166 0 0 0
T4 2186 0 0 0
T5 42906 0 0 0
T6 817 0 0 0
T8 3085 0 0 0
T9 1444 4 0 1
T10 0 3 0 1
T17 0 3 0 1
T19 1073 3 0 1
T20 2395 0 0 0
T30 0 62 0 1
T33 0 20 0 1
T73 0 4 0 1
T74 0 4 0 1

gen_edn_if_asserts[4].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 10897742 0 0
T1 2889 2836 0 0
T2 1812 1715 0 0
T3 1166 990 0 0
T4 2186 2068 0 0
T5 42906 21480 0 0
T6 817 674 0 0
T8 3085 3035 0 0
T9 1444 1376 0 0
T19 1073 1018 0 0
T20 2395 2323 0 0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 154982 0 0
T3 1166 7 0 0
T4 2186 1093 0 0
T5 42906 14635 0 0
T6 817 324 0 0
T7 0 328 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T13 0 22074 0 0
T18 0 718 0 0
T19 1073 0 0 0
T20 2395 0 0 0
T31 2401 0 0 0
T43 1628 0 0 0
T46 0 1101 0 0
T66 0 1102 0 0
T67 0 362 0 0

gen_edn_if_asserts[5].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 572226 0 280
T1 2889 548 0 0
T2 1812 12 0 0
T3 1166 512 0 0
T4 2186 1448 0 0
T5 42906 16063 0 2
T6 817 363 0 0
T8 3085 395 0 0
T9 1444 134 0 0
T13 0 0 0 2
T19 1073 73 0 0
T20 2395 343 0 0
T27 0 0 0 2
T28 0 0 0 2
T29 0 0 0 2
T56 0 0 0 2
T57 0 0 0 2
T58 0 0 0 2
T59 0 0 0 2
T60 0 0 0 2

gen_edn_if_asserts[5].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 2374 0 99
T2 1812 61 0 1
T3 1166 0 0 0
T4 2186 0 0 0
T5 42906 0 0 0
T6 817 0 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T10 0 0 0 1
T19 1073 0 0 0
T20 2395 0 0 0
T30 0 49 0 1
T31 2401 0 0 0
T33 0 23 0 1
T37 0 17 0 1
T39 0 4 0 1
T57 0 4 0 0
T69 0 0 0 1
T71 0 4 0 0
T74 0 4 0 0
T75 0 3 0 1
T76 0 4 0 1
T77 0 0 0 1

gen_edn_if_asserts[5].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 10897742 0 0
T1 2889 2836 0 0
T2 1812 1715 0 0
T3 1166 990 0 0
T4 2186 2068 0 0
T5 42906 21480 0 0
T6 817 674 0 0
T8 3085 3035 0 0
T9 1444 1376 0 0
T19 1073 1018 0 0
T20 2395 2323 0 0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 154982 0 0
T3 1166 7 0 0
T4 2186 1093 0 0
T5 42906 14635 0 0
T6 817 324 0 0
T7 0 328 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T13 0 22074 0 0
T18 0 718 0 0
T19 1073 0 0 0
T20 2395 0 0 0
T31 2401 0 0 0
T43 1628 0 0 0
T46 0 1101 0 0
T66 0 1102 0 0
T67 0 362 0 0

gen_edn_if_asserts[6].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 572226 0 280
T1 2889 548 0 0
T2 1812 12 0 0
T3 1166 512 0 0
T4 2186 1448 0 0
T5 42906 16063 0 2
T6 817 363 0 0
T8 3085 395 0 0
T9 1444 134 0 0
T13 0 0 0 2
T19 1073 73 0 0
T20 2395 343 0 0
T27 0 0 0 2
T28 0 0 0 2
T29 0 0 0 2
T56 0 0 0 2
T57 0 0 0 2
T58 0 0 0 2
T59 0 0 0 2
T60 0 0 0 2

gen_edn_if_asserts[6].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 2201 0 86
T2 1812 3 0 1
T3 1166 0 0 0
T4 2186 0 0 0
T5 42906 0 0 0
T6 817 0 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T10 0 15 0 1
T17 0 3 0 1
T19 1073 0 0 0
T20 2395 0 0 0
T30 0 21 0 1
T31 2401 0 0 0
T37 0 3 0 1
T40 0 4 0 1
T41 0 38 0 1
T42 0 3 0 1
T78 0 4 0 1
T79 0 4 0 0
T80 0 0 0 1

gen_edn_if_asserts[6].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 10897742 0 0
T1 2889 2836 0 0
T2 1812 1715 0 0
T3 1166 990 0 0
T4 2186 2068 0 0
T5 42906 21480 0 0
T6 817 674 0 0
T8 3085 3035 0 0
T9 1444 1376 0 0
T19 1073 1018 0 0
T20 2395 2323 0 0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11097801 154982 0 0
T3 1166 7 0 0
T4 2186 1093 0 0
T5 42906 14635 0 0
T6 817 324 0 0
T7 0 328 0 0
T8 3085 0 0 0
T9 1444 0 0 0
T13 0 22074 0 0
T18 0 718 0 0
T19 1073 0 0 0
T20 2395 0 0 0
T31 2401 0 0 0
T43 1628 0 0 0
T46 0 1101 0 0
T66 0 1102 0 0
T67 0 362 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%