Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11613296	412147	0	0
boot_gen_cmd_rd_A	11613296	2886	0	0
boot_ins_cmd_rd_A	11613296	3393	0	0
ctrl_rd_A	11613296	2862	0	0
err_code_test_rd_A	11613296	3292	0	0
intr_enable_rd_A	11613296	7304	0	0
max_num_reqs_between_reseeds_rd_A	11613296	3725	0	0
regwen_rd_A	11613296	4157	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11613296	412147	0	0
T27	338087	12919	0	0
T28	168919	7199	0	0
T29	0	18108	0	0
T34	2230	0	0	0
T68	2001	0	0	0
T69	1110	0	0	0
T75	1494	0	0	0
T76	1988	0	0	0
T77	2024	0	0	0
T94	22556	0	0	0
T98	0	18932	0	0
T218	0	9266	0	0
T219	0	13836	0	0
T220	0	4648	0	0
T221	0	19928	0	0
T222	0	7633	0	0
T223	0	18408	0	0
T224	3076	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11613296	2886	0	0
T27	338087	172	0	0
T28	168919	121	0	0
T34	2230	0	0	0
T68	2001	0	0	0
T69	1110	0	0	0
T75	1494	0	0	0
T76	1988	0	0	0
T77	2024	0	0	0
T94	22556	0	0	0
T224	3076	0	0	0
T225	0	143	0	0
T226	0	428	0	0
T227	0	416	0	0
T228	0	499	0	0
T229	0	350	0	0
T230	0	52	0	0
T231	0	125	0	0
T232	0	104	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11613296	3393	0	0
T27	338087	247	0	0
T28	168919	129	0	0
T34	2230	0	0	0
T68	2001	0	0	0
T69	1110	0	0	0
T75	1494	0	0	0
T76	1988	0	0	0
T77	2024	0	0	0
T94	22556	0	0	0
T224	3076	0	0	0
T225	0	160	0	0
T226	0	587	0	0
T227	0	503	0	0
T228	0	548	0	0
T229	0	487	0	0
T230	0	47	0	0
T231	0	195	0	0
T232	0	65	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11613296	2862	0	0
T1	2889	1	0	0
T2	1812	0	0	0
T3	1166	0	0	0
T4	2186	0	0	0
T5	42906	0	0	0
T6	817	0	0	0
T7	0	7	0	0
T8	3085	0	0	0
T9	1444	0	0	0
T19	1073	0	0	0
T20	2395	0	0	0
T21	0	22	0	0
T27	0	164	0	0
T28	0	86	0	0
T85	0	16	0	0
T110	0	10	0	0
T125	0	1	0	0
T233	0	4	0	0
T234	0	2	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11613296	3292	0	0
T27	338087	194	0	0
T28	168919	166	0	0
T34	2230	0	0	0
T68	2001	0	0	0
T69	1110	0	0	0
T75	1494	0	0	0
T76	1988	0	0	0
T77	2024	0	0	0
T94	22556	0	0	0
T224	3076	0	0	0
T225	0	262	0	0
T226	0	498	0	0
T227	0	439	0	0
T228	0	555	0	0
T229	0	422	0	0
T230	0	34	0	0
T231	0	172	0	0
T232	0	72	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11613296	7304	0	0
T7	1505	0	0	0
T21	0	7	0	0
T27	0	371	0	0
T28	0	260	0	0
T39	1897	0	0	0
T44	21708	117	0	0
T46	2131	0	0	0
T61	1566	0	0	0
T62	1409	0	0	0
T63	11613	0	0	0
T64	1494	0	0	0
T65	3799	0	0	0
T66	1825	0	0	0
T234	0	106	0	0
T235	0	17	0	0
T236	0	150	0	0
T237	0	27	0	0
T238	0	66	0	0
T239	0	91	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11613296	3725	0	0
T27	338087	186	0	0
T28	168919	94	0	0
T34	2230	0	0	0
T68	2001	0	0	0
T69	1110	0	0	0
T75	1494	0	0	0
T76	1988	0	0	0
T77	2024	0	0	0
T94	22556	0	0	0
T224	3076	0	0	0
T225	0	159	0	0
T226	0	380	0	0
T227	0	343	0	0
T228	0	592	0	0
T229	0	319	0	0
T230	0	54	0	0
T231	0	130	0	0
T232	0	60	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11613296	4157	0	0
T27	338087	247	0	0
T28	168919	130	0	0
T34	2230	0	0	0
T68	2001	0	0	0
T69	1110	0	0	0
T75	1494	0	0	0
T76	1988	0	0	0
T77	2024	0	0	0
T94	22556	0	0	0
T224	3076	0	0	0
T225	0	174	0	0
T226	0	514	0	0
T227	0	406	0	0
T228	0	566	0	0
T229	0	449	0	0
T230	0	42	0	0
T231	0	259	0	0
T232	0	48	0	0