Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.11	98.25	93.97	97.02	91.28	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.03	99.92	92.75	82.54	91.28	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T29,T28,T30

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T16,T17
1	0	Covered	T5,T31,T6

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T2,T4,T38	Yes	T2,T4,T38	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
edn_i[1].edn_req	Yes	Yes	T20,T8,T23	Yes	T20,T8,T23	INPUT
edn_i[2].edn_req	Yes	Yes	T20,T23,T13	Yes	T20,T23,T13	INPUT
edn_i[3].edn_req	Yes	Yes	T3,T20,T5	Yes	T3,T20,T5	INPUT
edn_i[4].edn_req	Yes	Yes	T20,T13,T39	Yes	T20,T13,T39	INPUT
edn_i[5].edn_req	Yes	Yes	T20,T22,T29	Yes	T20,T22,T29	INPUT
edn_i[6].edn_req	Yes	Yes	T1,T31,T13	Yes	T1,T31,T13	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T4,T8,T24	Yes	T3,T4,T8	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T23,T30,T40	Yes	T20,T8,T23	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T40,T41,T42	Yes	T20,T8,T30	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T20,T8,T23	Yes	T20,T8,T23	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T20,T30,T43	Yes	T20,T23,T30	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T20,T30,T44	Yes	T20,T30,T43	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T20,T23,T30	Yes	T20,T23,T30	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T3,T20,T23	Yes	T3,T20,T23	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T3,T44,T9	Yes	T3,T20,T23	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T3,T20,T23	Yes	T3,T20,T23	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T20,T39,T43	Yes	T20,T39,T43	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T20,T39,T43	Yes	T20,T39,T43	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T20,T39,T43	Yes	T20,T39,T43	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T20,T22,T27	Yes	T20,T22,T27	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T20,T9,T45	Yes	T20,T22,T43	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T20,T22,T29	Yes	T20,T22,T29	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T31,T19,T41	Yes	T1,T31,T19	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T31,T19,T41	Yes	T1,T31,T19	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T1,T31,T19	Yes	T1,T31,T19	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T3,T4,T20	Yes	T3,T4,T20	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T3,T4,T20	Yes	T3,T4,T20	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T28,T46,T47	Yes	T28,T46,T47	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T21,T29,T28	Yes	T21,T29,T28	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T21,T5,T31	Yes	T21,T5,T31	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T21,T29,T28	Yes	T21,T29,T28	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T21,T5,T31	Yes	T21,T5,T31	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T2,T4,T24	Yes	T2,T4,T24	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T2,T4,T31	Yes	T2,T4,T31	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	10084005	9907209	0	0
CsrngAppIfOut_A	10084005	9907209	0	0
FpvSecCmCntAlertCheck_A	10084005	109	0	0
FpvSecCmGenCmdFifoRptrCheck_A	10084005	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	10084005	70	0	0
FpvSecCmMainFsmCheck_A	10084005	70	0	0
FpvSecCmRegWeOnehotCheck_A	10084005	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	10084005	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	10084005	70	0	0
IntrEdnCmdReqDoneKnownO_A	10084005	9907209	0	0
TlAReadyKnownO_A	10084005	9907209	0	0
TlDValidKnownO_A	10084005	9907209	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	10084005	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	10084005	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	10084005	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	10084005	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	10084005	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	10084005	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	10084005	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	10084005	584871	0	292
gen_edn_if_asserts[0].EdnDataStable_A	10084005	74633	0	430
gen_edn_if_asserts[0].EdnEndPointOut_A	10084005	9907209	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	10084005	165647	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	10084005	584871	0	292
gen_edn_if_asserts[1].EdnDataStable_A	10084005	4931	0	132
gen_edn_if_asserts[1].EdnEndPointOut_A	10084005	9907209	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	10084005	165647	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	10084005	584871	0	292
gen_edn_if_asserts[2].EdnDataStable_A	10084005	2611	0	113
gen_edn_if_asserts[2].EdnEndPointOut_A	10084005	9907209	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	10084005	165647	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	10084005	584871	0	292
gen_edn_if_asserts[3].EdnDataStable_A	10084005	3262	0	90
gen_edn_if_asserts[3].EdnEndPointOut_A	10084005	9907209	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	10084005	165647	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	10084005	584871	0	292
gen_edn_if_asserts[4].EdnDataStable_A	10084005	4340	0	87
gen_edn_if_asserts[4].EdnEndPointOut_A	10084005	9907209	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	10084005	165647	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	10084005	584871	0	292
gen_edn_if_asserts[5].EdnDataStable_A	10084005	3401	0	89
gen_edn_if_asserts[5].EdnEndPointOut_A	10084005	9907209	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	10084005	165647	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	10084005	584871	0	292
gen_edn_if_asserts[6].EdnDataStable_A	10084005	2902	0	83
gen_edn_if_asserts[6].EdnEndPointOut_A	10084005	9907209	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	10084005	165647	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	9907209	0	0
T1	1043	964	0	0
T2	103705	103608	0	0
T3	2400	2350	0	0
T4	240398	240287	0	0
T5	2525	2420	0	0
T8	6685	6600	0	0
T20	1934	1881	0	0
T21	1231	1158	0	0
T22	918	819	0	0
T23	3689	3620	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	9907209	0	0
T1	1043	964	0	0
T2	103705	103608	0	0
T3	2400	2350	0	0
T4	240398	240287	0	0
T5	2525	2420	0	0
T8	6685	6600	0	0
T20	1934	1881	0	0
T21	1231	1158	0	0
T22	918	819	0	0
T23	3689	3620	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	109	0	0
T12	2470	0	0	0
T13	67924	20	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	10	0	0
T24	16448	0	0	0
T30	2100	0	0	0
T39	1884	0	0	0
T40	779	0	0	0
T43	1451	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	1730	0	0	0
T55	1352	0	0	0
T56	1578	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	70	0	0
T12	2470	0	0	0
T13	67924	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T24	16448	0	0	0
T30	2100	0	0	0
T39	1884	0	0	0
T40	779	0	0	0
T43	1451	0	0	0
T54	1730	0	0	0
T55	1352	0	0	0
T56	1578	0	0	0
T57	0	10	0	0
T58	0	20	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	70	0	0
T12	2470	0	0	0
T13	67924	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T24	16448	0	0	0
T30	2100	0	0	0
T39	1884	0	0	0
T40	779	0	0	0
T43	1451	0	0	0
T54	1730	0	0	0
T55	1352	0	0	0
T56	1578	0	0	0
T57	0	10	0	0
T58	0	20	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	70	0	0
T12	2470	0	0	0
T13	67924	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T24	16448	0	0	0
T30	2100	0	0	0
T39	1884	0	0	0
T40	779	0	0	0
T43	1451	0	0	0
T54	1730	0	0	0
T55	1352	0	0	0
T56	1578	0	0	0
T57	0	10	0	0
T58	0	20	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	70	0	0
T12	2470	0	0	0
T13	67924	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T24	16448	0	0	0
T30	2100	0	0	0
T39	1884	0	0	0
T40	779	0	0	0
T43	1451	0	0	0
T54	1730	0	0	0
T55	1352	0	0	0
T56	1578	0	0	0
T57	0	10	0	0
T58	0	20	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	70	0	0
T12	2470	0	0	0
T13	67924	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T24	16448	0	0	0
T30	2100	0	0	0
T39	1884	0	0	0
T40	779	0	0	0
T43	1451	0	0	0
T54	1730	0	0	0
T55	1352	0	0	0
T56	1578	0	0	0
T57	0	10	0	0
T58	0	20	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	70	0	0
T12	2470	0	0	0
T13	67924	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T24	16448	0	0	0
T30	2100	0	0	0
T39	1884	0	0	0
T40	779	0	0	0
T43	1451	0	0	0
T54	1730	0	0	0
T55	1352	0	0	0
T56	1578	0	0	0
T57	0	10	0	0
T58	0	20	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	9907209	0	0
T1	1043	964	0	0
T2	103705	103608	0	0
T3	2400	2350	0	0
T4	240398	240287	0	0
T5	2525	2420	0	0
T8	6685	6600	0	0
T20	1934	1881	0	0
T21	1231	1158	0	0
T22	918	819	0	0
T23	3689	3620	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	9907209	0	0
T1	1043	964	0	0
T2	103705	103608	0	0
T3	2400	2350	0	0
T4	240398	240287	0	0
T5	2525	2420	0	0
T8	6685	6600	0	0
T20	1934	1881	0	0
T21	1231	1158	0	0
T22	918	819	0	0
T23	3689	3620	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	9907209	0	0
T1	1043	964	0	0
T2	103705	103608	0	0
T3	2400	2350	0	0
T4	240398	240287	0	0
T5	2525	2420	0	0
T8	6685	6600	0	0
T20	1934	1881	0	0
T21	1231	1158	0	0
T22	918	819	0	0
T23	3689	3620	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	70	0	0
T12	2470	0	0	0
T13	67924	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T24	16448	0	0	0
T30	2100	0	0	0
T39	1884	0	0	0
T40	779	0	0	0
T43	1451	0	0	0
T54	1730	0	0	0
T55	1352	0	0	0
T56	1578	0	0	0
T57	0	10	0	0
T58	0	20	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	70	0	0
T12	2470	0	0	0
T13	67924	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T24	16448	0	0	0
T30	2100	0	0	0
T39	1884	0	0	0
T40	779	0	0	0
T43	1451	0	0	0
T54	1730	0	0	0
T55	1352	0	0	0
T56	1578	0	0	0
T57	0	10	0	0
T58	0	20	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	70	0	0
T12	2470	0	0	0
T13	67924	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T24	16448	0	0	0
T30	2100	0	0	0
T39	1884	0	0	0
T40	779	0	0	0
T43	1451	0	0	0
T54	1730	0	0	0
T55	1352	0	0	0
T56	1578	0	0	0
T57	0	10	0	0
T58	0	20	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	70	0	0
T12	2470	0	0	0
T13	67924	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T24	16448	0	0	0
T30	2100	0	0	0
T39	1884	0	0	0
T40	779	0	0	0
T43	1451	0	0	0
T54	1730	0	0	0
T55	1352	0	0	0
T56	1578	0	0	0
T57	0	10	0	0
T58	0	20	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	70	0	0
T12	2470	0	0	0
T13	67924	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T24	16448	0	0	0
T30	2100	0	0	0
T39	1884	0	0	0
T40	779	0	0	0
T43	1451	0	0	0
T54	1730	0	0	0
T55	1352	0	0	0
T56	1578	0	0	0
T57	0	10	0	0
T58	0	20	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	70	0	0
T12	2470	0	0	0
T13	67924	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T24	16448	0	0	0
T30	2100	0	0	0
T39	1884	0	0	0
T40	779	0	0	0
T43	1451	0	0	0
T54	1730	0	0	0
T55	1352	0	0	0
T56	1578	0	0	0
T57	0	10	0	0
T58	0	20	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	70	0	0
T12	2470	0	0	0
T13	67924	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T24	16448	0	0	0
T30	2100	0	0	0
T39	1884	0	0	0
T40	779	0	0	0
T43	1451	0	0	0
T54	1730	0	0	0
T55	1352	0	0	0
T56	1578	0	0	0
T57	0	10	0	0
T58	0	20	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	584871	0	292
T1	1043	97	0	0
T2	103705	1386	0	2
T3	2400	267	0	0
T4	240398	4034	0	2
T5	2525	1612	0	0
T8	6685	65	0	0
T12	0	0	0	2
T13	0	0	0	2
T20	1934	10	0	0
T21	1231	1156	0	2
T22	918	70	0	0
T23	3689	16	0	0
T55	0	0	0	2
T56	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	74633	0	430
T2	103705	3	0	0
T3	2400	3	0	1
T4	240398	52	0	0
T5	2525	0	0	0
T8	6685	1249	0	1
T20	1934	3	0	1
T21	1231	0	0	0
T22	918	0	0	0
T23	3689	4	0	1
T24	0	33	0	1
T28	0	4	0	1
T29	2509	0	0	0
T39	0	3	0	1
T43	0	0	0	1
T54	0	7	0	1
T62	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	9907209	0	0
T1	1043	964	0	0
T2	103705	103608	0	0
T3	2400	2350	0	0
T4	240398	240287	0	0
T5	2525	2420	0	0
T8	6685	6600	0	0
T20	1934	1881	0	0
T21	1231	1158	0	0
T22	918	819	0	0
T23	3689	3620	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	165647	0	0
T5	2525	1135	0	0
T6	2054	1102	0	0
T7	0	612	0	0
T8	6685	0	0	0
T13	67924	22515	0	0
T14	0	594	0	0
T15	0	632	0	0
T22	918	0	0	0
T23	3689	0	0	0
T27	1335	0	0	0
T28	2751	0	0	0
T29	2509	0	0	0
T31	1980	19	0	0
T32	0	24	0	0
T40	0	247	0	0
T63	0	7	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	584871	0	292
T1	1043	97	0	0
T2	103705	1386	0	2
T3	2400	267	0	0
T4	240398	4034	0	2
T5	2525	1612	0	0
T8	6685	65	0	0
T12	0	0	0	2
T13	0	0	0	2
T20	1934	10	0	0
T21	1231	1156	0	2
T22	918	70	0	0
T23	3689	16	0	0
T55	0	0	0	2
T56	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	4931	0	132
T5	2525	0	0	0
T6	2054	0	0	0
T8	6685	3	0	1
T9	0	3	0	1
T20	1934	3	0	1
T21	1231	0	0	0
T22	918	0	0	0
T23	3689	3	0	1
T28	2751	0	0	0
T29	2509	0	0	0
T30	0	4	0	1
T31	1980	0	0	0
T32	0	1	0	0
T40	0	1	0	0
T41	0	63	0	1
T42	0	0	0	1
T48	0	1	0	0
T64	0	4	0	0
T65	0	0	0	1
T66	0	0	0	1
T67	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	9907209	0	0
T1	1043	964	0	0
T2	103705	103608	0	0
T3	2400	2350	0	0
T4	240398	240287	0	0
T5	2525	2420	0	0
T8	6685	6600	0	0
T20	1934	1881	0	0
T21	1231	1158	0	0
T22	918	819	0	0
T23	3689	3620	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	165647	0	0
T5	2525	1135	0	0
T6	2054	1102	0	0
T7	0	612	0	0
T8	6685	0	0	0
T13	67924	22515	0	0
T14	0	594	0	0
T15	0	632	0	0
T22	918	0	0	0
T23	3689	0	0	0
T27	1335	0	0	0
T28	2751	0	0	0
T29	2509	0	0	0
T31	1980	19	0	0
T32	0	24	0	0
T40	0	247	0	0
T63	0	7	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	584871	0	292
T1	1043	97	0	0
T2	103705	1386	0	2
T3	2400	267	0	0
T4	240398	4034	0	2
T5	2525	1612	0	0
T8	6685	65	0	0
T12	0	0	0	2
T13	0	0	0	2
T20	1934	10	0	0
T21	1231	1156	0	2
T22	918	70	0	0
T23	3689	16	0	0
T55	0	0	0	2
T56	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	2611	0	113
T5	2525	0	0	0
T6	2054	0	0	0
T8	6685	0	0	0
T9	0	3	0	1
T20	1934	27	0	1
T21	1231	0	0	0
T22	918	0	0	0
T23	3689	3	0	1
T28	2751	0	0	0
T29	2509	0	0	0
T30	0	4	0	0
T31	1980	0	0	0
T43	0	3	0	1
T44	0	47	0	1
T45	0	0	0	1
T63	0	1	0	0
T65	0	3	0	1
T67	0	0	0	1
T68	0	3	0	1
T69	0	4	0	0
T70	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	9907209	0	0
T1	1043	964	0	0
T2	103705	103608	0	0
T3	2400	2350	0	0
T4	240398	240287	0	0
T5	2525	2420	0	0
T8	6685	6600	0	0
T20	1934	1881	0	0
T21	1231	1158	0	0
T22	918	819	0	0
T23	3689	3620	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	165647	0	0
T5	2525	1135	0	0
T6	2054	1102	0	0
T7	0	612	0	0
T8	6685	0	0	0
T13	67924	22515	0	0
T14	0	594	0	0
T15	0	632	0	0
T22	918	0	0	0
T23	3689	0	0	0
T27	1335	0	0	0
T28	2751	0	0	0
T29	2509	0	0	0
T31	1980	19	0	0
T32	0	24	0	0
T40	0	247	0	0
T63	0	7	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	584871	0	292
T1	1043	97	0	0
T2	103705	1386	0	2
T3	2400	267	0	0
T4	240398	4034	0	2
T5	2525	1612	0	0
T8	6685	65	0	0
T12	0	0	0	2
T13	0	0	0	2
T20	1934	10	0	0
T21	1231	1156	0	2
T22	918	70	0	0
T23	3689	16	0	0
T55	0	0	0	2
T56	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	3262	0	90
T3	2400	18	0	1
T4	240398	0	0	0
T5	2525	0	0	0
T8	6685	0	0	0
T9	0	13	0	1
T20	1934	3	0	1
T21	1231	0	0	0
T22	918	0	0	0
T23	3689	3	0	1
T29	2509	0	0	0
T31	1980	0	0	0
T44	0	30	0	1
T56	0	4	0	0
T67	0	0	0	1
T70	0	3	0	1
T71	0	4	0	1
T72	0	3	0	1
T73	0	4	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	9907209	0	0
T1	1043	964	0	0
T2	103705	103608	0	0
T3	2400	2350	0	0
T4	240398	240287	0	0
T5	2525	2420	0	0
T8	6685	6600	0	0
T20	1934	1881	0	0
T21	1231	1158	0	0
T22	918	819	0	0
T23	3689	3620	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	165647	0	0
T5	2525	1135	0	0
T6	2054	1102	0	0
T7	0	612	0	0
T8	6685	0	0	0
T13	67924	22515	0	0
T14	0	594	0	0
T15	0	632	0	0
T22	918	0	0	0
T23	3689	0	0	0
T27	1335	0	0	0
T28	2751	0	0	0
T29	2509	0	0	0
T31	1980	19	0	0
T32	0	24	0	0
T40	0	247	0	0
T63	0	7	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	584871	0	292
T1	1043	97	0	0
T2	103705	1386	0	2
T3	2400	267	0	0
T4	240398	4034	0	2
T5	2525	1612	0	0
T8	6685	65	0	0
T12	0	0	0	2
T13	0	0	0	2
T20	1934	10	0	0
T21	1231	1156	0	2
T22	918	70	0	0
T23	3689	16	0	0
T55	0	0	0	2
T56	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	4340	0	87
T5	2525	0	0	0
T6	2054	0	0	0
T8	6685	0	0	0
T9	0	3	0	1
T20	1934	5	0	1
T21	1231	0	0	0
T22	918	0	0	0
T23	3689	0	0	0
T28	2751	0	0	0
T29	2509	0	0	0
T31	1980	0	0	0
T39	0	44	0	1
T43	0	25	0	1
T65	0	14	0	1
T67	0	0	0	1
T68	0	3	0	1
T74	0	4	0	1
T75	0	5	0	0
T76	0	4	0	1
T77	0	4	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	9907209	0	0
T1	1043	964	0	0
T2	103705	103608	0	0
T3	2400	2350	0	0
T4	240398	240287	0	0
T5	2525	2420	0	0
T8	6685	6600	0	0
T20	1934	1881	0	0
T21	1231	1158	0	0
T22	918	819	0	0
T23	3689	3620	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	165647	0	0
T5	2525	1135	0	0
T6	2054	1102	0	0
T7	0	612	0	0
T8	6685	0	0	0
T13	67924	22515	0	0
T14	0	594	0	0
T15	0	632	0	0
T22	918	0	0	0
T23	3689	0	0	0
T27	1335	0	0	0
T28	2751	0	0	0
T29	2509	0	0	0
T31	1980	19	0	0
T32	0	24	0	0
T40	0	247	0	0
T63	0	7	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	584871	0	292
T1	1043	97	0	0
T2	103705	1386	0	2
T3	2400	267	0	0
T4	240398	4034	0	2
T5	2525	1612	0	0
T8	6685	65	0	0
T12	0	0	0	2
T13	0	0	0	2
T20	1934	10	0	0
T21	1231	1156	0	2
T22	918	70	0	0
T23	3689	16	0	0
T55	0	0	0	2
T56	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	3401	0	89
T5	2525	0	0	0
T6	2054	0	0	0
T8	6685	0	0	0
T9	0	40	0	1
T20	1934	59	0	1
T21	1231	0	0	0
T22	918	3	0	1
T23	3689	0	0	0
T27	0	3	0	1
T28	2751	0	0	0
T29	2509	4	0	1
T31	1980	0	0	0
T41	0	3	0	1
T43	0	9	0	1
T45	0	891	0	1
T60	0	4	0	0
T65	0	3	0	1
T78	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	9907209	0	0
T1	1043	964	0	0
T2	103705	103608	0	0
T3	2400	2350	0	0
T4	240398	240287	0	0
T5	2525	2420	0	0
T8	6685	6600	0	0
T20	1934	1881	0	0
T21	1231	1158	0	0
T22	918	819	0	0
T23	3689	3620	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	165647	0	0
T5	2525	1135	0	0
T6	2054	1102	0	0
T7	0	612	0	0
T8	6685	0	0	0
T13	67924	22515	0	0
T14	0	594	0	0
T15	0	632	0	0
T22	918	0	0	0
T23	3689	0	0	0
T27	1335	0	0	0
T28	2751	0	0	0
T29	2509	0	0	0
T31	1980	19	0	0
T32	0	24	0	0
T40	0	247	0	0
T63	0	7	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	584871	0	292
T1	1043	97	0	0
T2	103705	1386	0	2
T3	2400	267	0	0
T4	240398	4034	0	2
T5	2525	1612	0	0
T8	6685	65	0	0
T12	0	0	0	2
T13	0	0	0	2
T20	1934	10	0	0
T21	1231	1156	0	2
T22	918	70	0	0
T23	3689	16	0	0
T55	0	0	0	2
T56	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	2902	0	83
T1	1043	3	0	1
T2	103705	0	0	0
T3	2400	0	0	0
T4	240398	0	0	0
T5	2525	0	0	0
T8	6685	0	0	0
T9	0	15	0	1
T10	0	0	0	1
T19	0	15	0	1
T20	1934	0	0	0
T21	1231	0	0	0
T22	918	0	0	0
T23	3689	0	0	0
T31	0	1	0	0
T41	0	12	0	1
T42	0	15	0	1
T51	0	1	0	0
T79	0	4	0	1
T80	0	4	0	1
T81	0	4	0	1
T82	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	9907209	0	0
T1	1043	964	0	0
T2	103705	103608	0	0
T3	2400	2350	0	0
T4	240398	240287	0	0
T5	2525	2420	0	0
T8	6685	6600	0	0
T20	1934	1881	0	0
T21	1231	1158	0	0
T22	918	819	0	0
T23	3689	3620	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	165647	0	0
T5	2525	1135	0	0
T6	2054	1102	0	0
T7	0	612	0	0
T8	6685	0	0	0
T13	67924	22515	0	0
T14	0	594	0	0
T15	0	632	0	0
T22	918	0	0	0
T23	3689	0	0	0
T27	1335	0	0	0
T28	2751	0	0	0
T29	2509	0	0	0
T31	1980	19	0	0
T32	0	24	0	0
T40	0	247	0	0
T63	0	7	0	0