Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	10578691	354538	0	0
boot_gen_cmd_rd_A	10578691	2170	0	0
boot_ins_cmd_rd_A	10578691	2555	0	0
ctrl_rd_A	10578691	2393	0	0
err_code_test_rd_A	10578691	2527	0	0
intr_enable_rd_A	10578691	5070	0	0
max_num_reqs_between_reseeds_rd_A	10578691	3001	0	0
regwen_rd_A	10578691	3072	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10578691	354538	0	0
T2	103705	7085	0	0
T3	2400	0	0	0
T4	240398	9706	0	0
T5	2525	0	0	0
T8	6685	0	0	0
T20	1934	0	0	0
T21	1231	0	0	0
T22	918	0	0	0
T23	3689	0	0	0
T29	2509	0	0	0
T38	0	5358	0	0
T90	0	7536	0	0
T92	0	4942	0	0
T209	0	5192	0	0
T210	0	12149	0	0
T211	0	5300	0	0
T212	0	13435	0	0
T213	0	19356	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10578691	2170	0	0
T42	4424	0	0	0
T51	2310	0	0	0
T52	1751	0	0	0
T67	4526	0	0	0
T84	1290	0	0	0
T92	135419	216	0	0
T143	2684	0	0	0
T163	2747	0	0	0
T210	0	295	0	0
T212	0	188	0	0
T214	0	224	0	0
T215	0	132	0	0
T216	0	113	0	0
T217	0	216	0	0
T218	0	228	0	0
T219	0	181	0	0
T220	0	14	0	0
T221	1283	0	0	0
T222	5823	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10578691	2555	0	0
T42	4424	0	0	0
T51	2310	0	0	0
T52	1751	0	0	0
T67	4526	0	0	0
T84	1290	0	0	0
T92	135419	164	0	0
T143	2684	0	0	0
T163	2747	0	0	0
T210	0	421	0	0
T212	0	278	0	0
T214	0	249	0	0
T215	0	211	0	0
T216	0	82	0	0
T217	0	173	0	0
T218	0	265	0	0
T219	0	262	0	0
T221	1283	0	0	0
T222	5823	0	0	0
T223	0	9	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10578691	2393	0	0
T7	1283	0	0	0
T15	1217	0	0	0
T19	1730	0	0	0
T46	1607	0	0	0
T63	1117	0	0	0
T68	1786	0	0	0
T75	0	1	0	0
T92	0	182	0	0
T105	1572	0	0	0
T210	0	362	0	0
T212	0	251	0	0
T214	0	224	0	0
T224	3935	2	0	0
T225	0	4	0	0
T226	0	4	0	0
T227	0	3	0	0
T228	0	5	0	0
T229	1284	0	0	0
T230	1440	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10578691	2527	0	0
T42	4424	0	0	0
T51	2310	0	0	0
T52	1751	0	0	0
T67	4526	0	0	0
T84	1290	0	0	0
T92	135419	175	0	0
T143	2684	0	0	0
T163	2747	0	0	0
T210	0	395	0	0
T212	0	276	0	0
T214	0	296	0	0
T215	0	212	0	0
T216	0	83	0	0
T217	0	207	0	0
T218	0	191	0	0
T219	0	271	0	0
T220	0	32	0	0
T221	1283	0	0	0
T222	5823	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10578691	5070	0	0
T7	1283	0	0	0
T15	1217	0	0	0
T19	1730	0	0	0
T46	1607	0	0	0
T63	1117	0	0	0
T68	1786	0	0	0
T92	0	243	0	0
T105	1572	0	0	0
T210	0	630	0	0
T212	0	358	0	0
T214	0	529	0	0
T215	0	278	0	0
T224	3935	25	0	0
T229	1284	0	0	0
T230	1440	0	0	0
T231	0	12	0	0
T232	0	63	0	0
T233	0	101	0	0
T234	0	13	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10578691	3001	0	0
T42	4424	0	0	0
T51	2310	0	0	0
T52	1751	0	0	0
T67	4526	0	0	0
T84	1290	0	0	0
T92	135419	173	0	0
T143	2684	0	0	0
T163	2747	0	0	0
T210	0	404	0	0
T212	0	209	0	0
T214	0	202	0	0
T215	0	149	0	0
T216	0	102	0	0
T217	0	221	0	0
T218	0	208	0	0
T219	0	282	0	0
T221	1283	0	0	0
T222	5823	0	0	0
T235	0	9	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10578691	3072	0	0
T42	4424	0	0	0
T51	2310	0	0	0
T52	1751	0	0	0
T67	4526	0	0	0
T84	1290	0	0	0
T92	135419	191	0	0
T143	2684	0	0	0
T163	2747	0	0	0
T210	0	443	0	0
T212	0	258	0	0
T214	0	236	0	0
T215	0	200	0	0
T216	0	113	0	0
T217	0	163	0	0
T218	0	192	0	0
T219	0	212	0	0
T221	1283	0	0	0
T222	5823	0	0	0
T235	0	10	0	0