ENTROPY_SRC Simulation Results

Wednesday February 28 2024 23:53:28 UTC

GitHub Revision: 32ed2c4230

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 10708067410766204292161266966839433462058030635847883045650346145926493105783

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 73.799us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 77.704us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 3.000s 28.780us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 16.000s 1.537ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 6.000s 149.486us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 33.433us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 3.000s 28.780us 20 20 100.00
entropy_src_csr_aliasing 6.000s 149.486us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 4.000s 73.799us 50 50 100.00
entropy_src_rng 4.783m 10.100ms 298 300 99.33
entropy_src_fw_ov 2.650m 5.070ms 299 300 99.67
V2 firmware_mode entropy_src_fw_ov 2.650m 5.070ms 299 300 99.67
V2 rng_mode entropy_src_rng 4.783m 10.100ms 298 300 99.33
V2 rng_max_rate entropy_src_rng_max_rate 4.800m 10.016ms 400 400 100.00
V2 health_checks entropy_src_rng 4.783m 10.100ms 298 300 99.33
V2 conditioning entropy_src_rng 4.783m 10.100ms 298 300 99.33
V2 interrupts entropy_src_rng 4.783m 10.100ms 298 300 99.33
V2 alerts entropy_src_rng 4.783m 10.100ms 298 300 99.33
entropy_src_functional_alerts 5.000s 238.423us 50 50 100.00
V2 stress_all entropy_src_stress_all 10.000s 1.202ms 50 50 100.00
V2 functional_errors entropy_src_functional_errors 5.000s 48.683us 1000 1000 100.00
V2 intr_test entropy_src_intr_test 3.000s 26.527us 50 50 100.00
V2 alert_test entropy_src_alert_test 4.000s 53.125us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 59.052us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 59.052us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 77.704us 5 5 100.00
entropy_src_csr_rw 3.000s 28.780us 20 20 100.00
entropy_src_csr_aliasing 6.000s 149.486us 5 5 100.00
entropy_src_same_csr_outstanding 4.000s 120.818us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 77.704us 5 5 100.00
entropy_src_csr_rw 3.000s 28.780us 20 20 100.00
entropy_src_csr_aliasing 6.000s 149.486us 5 5 100.00
entropy_src_same_csr_outstanding 4.000s 120.818us 20 20 100.00
V2 TOTAL 2237 2240 99.87
V2S tl_intg_err entropy_src_sec_cm 4.000s 93.655us 5 5 100.00
entropy_src_tl_intg_err 7.000s 713.066us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.783m 10.100ms 298 300 99.33
entropy_src_cfg_regwen 4.000s 16.847us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.783m 10.100ms 298 300 99.33
V2S sec_cm_config_redun entropy_src_rng 4.783m 10.100ms 298 300 99.33
V2S sec_cm_intersig_mubi entropy_src_rng 4.783m 10.100ms 298 300 99.33
entropy_src_fw_ov 2.650m 5.070ms 299 300 99.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 5.000s 48.683us 1000 1000 100.00
entropy_src_sec_cm 4.000s 93.655us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 5.000s 48.683us 1000 1000 100.00
entropy_src_sec_cm 4.000s 93.655us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.783m 10.100ms 298 300 99.33
V2S sec_cm_ctr_redun entropy_src_functional_errors 5.000s 48.683us 1000 1000 100.00
entropy_src_sec_cm 4.000s 93.655us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 5.000s 48.683us 1000 1000 100.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 238.423us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 713.066us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.733m 10.035ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 22.000s 2.025ms 45 50 90.00
TOTAL 2512 2520 99.68

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 10 10 8 80.00
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.12 98.87 97.22 99.69 95.87 89.21 97.00 91.70 53.71

Failure Buckets

Past Results