ENTROPY_SRC Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: c187a82ee8

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 99.094us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 100.983us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 3.000s 84.359us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 9.000s 1.404ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 9.000s 422.017us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 508.829us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 3.000s 84.359us 20 20 100.00
entropy_src_csr_aliasing 9.000s 422.017us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 4.000s 99.094us 50 50 100.00
entropy_src_rng 5.600m 10.062ms 299 300 99.67
entropy_src_fw_ov 2.700m 5.033ms 289 300 96.33
V2 firmware_mode entropy_src_fw_ov 2.700m 5.033ms 289 300 96.33
V2 rng_mode entropy_src_rng 5.600m 10.062ms 299 300 99.67
V2 rng_max_rate entropy_src_rng_max_rate 9.700m 10.058ms 394 400 98.50
V2 health_checks entropy_src_rng 5.600m 10.062ms 299 300 99.67
V2 conditioning entropy_src_rng 5.600m 10.062ms 299 300 99.67
V2 interrupts entropy_src_rng 5.600m 10.062ms 299 300 99.67
V2 alerts entropy_src_rng 5.600m 10.062ms 299 300 99.67
entropy_src_functional_alerts 5.000s 112.159us 50 50 100.00
V2 stress_all entropy_src_stress_all 11.000s 877.656us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 10.967m 10.012ms 962 1000 96.20
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 27.000s 7.676ms 50 50 100.00
V2 intr_test entropy_src_intr_test 3.000s 36.973us 50 50 100.00
V2 alert_test entropy_src_alert_test 3.000s 54.121us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 6.000s 252.365us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 6.000s 252.365us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 100.983us 5 5 100.00
entropy_src_csr_rw 3.000s 84.359us 20 20 100.00
entropy_src_csr_aliasing 9.000s 422.017us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 225.330us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 100.983us 5 5 100.00
entropy_src_csr_rw 3.000s 84.359us 20 20 100.00
entropy_src_csr_aliasing 9.000s 422.017us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 225.330us 20 20 100.00
V2 TOTAL 2234 2290 97.55
V2S tl_intg_err entropy_src_sec_cm 4.000s 92.434us 5 5 100.00
entropy_src_tl_intg_err 7.000s 208.349us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 5.600m 10.062ms 299 300 99.67
entropy_src_cfg_regwen 3.000s 30.556us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 5.600m 10.062ms 299 300 99.67
V2S sec_cm_config_redun entropy_src_rng 5.600m 10.062ms 299 300 99.67
V2S sec_cm_intersig_mubi entropy_src_rng 5.600m 10.062ms 299 300 99.67
entropy_src_fw_ov 2.700m 5.033ms 289 300 96.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 10.967m 10.012ms 962 1000 96.20
entropy_src_sec_cm 4.000s 92.434us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 10.967m 10.012ms 962 1000 96.20
entropy_src_sec_cm 4.000s 92.434us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 5.600m 10.062ms 299 300 99.67
V2S sec_cm_ctr_redun entropy_src_functional_errors 10.967m 10.012ms 962 1000 96.20
entropy_src_sec_cm 4.000s 92.434us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 10.967m 10.012ms 962 1000 96.20
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 112.159us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 208.349us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 5.033m 10.045ms 49 50 98.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 49 50 98.00
Unmapped tests entropy_src_intr 23.000s 4.298ms 44 50 88.00
TOTAL 2507 2570 97.55

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 3 3 3 100.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.12 98.19 95.42 98.36 95.88 88.07 97.92 90.46 56.64

Failure Buckets

Past Results