ENTROPY_SRC Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: 0cdf265eaa

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 93.487us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 4.000s 213.767us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 3.000s 51.526us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 11.000s 307.266us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 6.000s 205.262us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 572.299us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 3.000s 51.526us 20 20 100.00
entropy_src_csr_aliasing 6.000s 205.262us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 4.000s 93.487us 50 50 100.00
entropy_src_rng 4.800m 10.016ms 300 300 100.00
entropy_src_fw_ov 2.317m 5.071ms 299 300 99.67
V2 firmware_mode entropy_src_fw_ov 2.317m 5.071ms 299 300 99.67
V2 rng_mode entropy_src_rng 4.800m 10.016ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 4.917m 8.574ms 25 400 6.25
V2 health_checks entropy_src_rng 4.800m 10.016ms 300 300 100.00
V2 conditioning entropy_src_rng 4.800m 10.016ms 300 300 100.00
V2 interrupts entropy_src_rng 4.800m 10.016ms 300 300 100.00
V2 alerts entropy_src_rng 4.800m 10.016ms 300 300 100.00
entropy_src_functional_alerts 5.000s 873.412us 50 50 100.00
V2 stress_all entropy_src_stress_all 10.000s 873.957us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 13.000s 283.402us 1000 1000 100.00
V2 intr_test entropy_src_intr_test 3.000s 21.175us 50 50 100.00
V2 alert_test entropy_src_alert_test 3.000s 20.873us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 128.410us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 128.410us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 4.000s 213.767us 5 5 100.00
entropy_src_csr_rw 3.000s 51.526us 20 20 100.00
entropy_src_csr_aliasing 6.000s 205.262us 5 5 100.00
entropy_src_same_csr_outstanding 4.000s 148.186us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 4.000s 213.767us 5 5 100.00
entropy_src_csr_rw 3.000s 51.526us 20 20 100.00
entropy_src_csr_aliasing 6.000s 205.262us 5 5 100.00
entropy_src_same_csr_outstanding 4.000s 148.186us 20 20 100.00
V2 TOTAL 1864 2240 83.21
V2S tl_intg_err entropy_src_sec_cm 4.000s 262.722us 5 5 100.00
entropy_src_tl_intg_err 6.000s 149.084us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.800m 10.016ms 300 300 100.00
entropy_src_cfg_regwen 4.000s 22.761us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.800m 10.016ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 4.800m 10.016ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 4.800m 10.016ms 300 300 100.00
entropy_src_fw_ov 2.317m 5.071ms 299 300 99.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 13.000s 283.402us 1000 1000 100.00
entropy_src_sec_cm 4.000s 262.722us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 13.000s 283.402us 1000 1000 100.00
entropy_src_sec_cm 4.000s 262.722us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.800m 10.016ms 300 300 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 13.000s 283.402us 1000 1000 100.00
entropy_src_sec_cm 4.000s 262.722us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 13.000s 283.402us 1000 1000 100.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 873.412us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 6.000s 149.084us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.633m 10.024ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 17.000s 1.106ms 46 50 92.00
TOTAL 2140 2520 84.92

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 10 10 8 80.00
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
83.70 98.35 95.88 98.33 95.79 89.36 96.94 91.62 45.88

Failure Buckets

Past Results