ENTROPY_SRC Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: c30684b3ca

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 16.000s 26.049us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 4.000s 160.024us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 8.000s 89.195us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 17.000s 15.395ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 239.235us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 55.652us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 8.000s 89.195us 20 20 100.00
entropy_src_csr_aliasing 8.000s 239.235us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 16.000s 26.049us 50 50 100.00
entropy_src_rng 4.817m 10.023ms 299 300 99.67
entropy_src_fw_ov 2.283m 5.097ms 298 300 99.33
V2 firmware_mode entropy_src_fw_ov 2.283m 5.097ms 298 300 99.33
V2 rng_mode entropy_src_rng 4.817m 10.023ms 299 300 99.67
V2 rng_max_rate entropy_src_rng_max_rate 6.333m 8.719ms 31 400 7.75
V2 health_checks entropy_src_rng 4.817m 10.023ms 299 300 99.67
V2 conditioning entropy_src_rng 4.817m 10.023ms 299 300 99.67
V2 interrupts entropy_src_rng 4.817m 10.023ms 299 300 99.67
V2 alerts entropy_src_rng 4.817m 10.023ms 299 300 99.67
entropy_src_functional_alerts 14.000s 75.293us 50 50 100.00
V2 stress_all entropy_src_stress_all 22.000s 250.177us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 21.000s 71.317us 1000 1000 100.00
V2 intr_test entropy_src_intr_test 8.000s 18.569us 50 50 100.00
V2 alert_test entropy_src_alert_test 15.000s 25.996us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 256.965us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 256.965us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 4.000s 160.024us 5 5 100.00
entropy_src_csr_rw 8.000s 89.195us 20 20 100.00
entropy_src_csr_aliasing 8.000s 239.235us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 80.671us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 4.000s 160.024us 5 5 100.00
entropy_src_csr_rw 8.000s 89.195us 20 20 100.00
entropy_src_csr_aliasing 8.000s 239.235us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 80.671us 20 20 100.00
V2 TOTAL 1868 2240 83.39
V2S tl_intg_err entropy_src_sec_cm 9.000s 163.821us 5 5 100.00
entropy_src_tl_intg_err 7.000s 177.478us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.817m 10.023ms 299 300 99.67
entropy_src_cfg_regwen 11.000s 270.883us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.817m 10.023ms 299 300 99.67
V2S sec_cm_config_redun entropy_src_rng 4.817m 10.023ms 299 300 99.67
V2S sec_cm_intersig_mubi entropy_src_rng 4.817m 10.023ms 299 300 99.67
entropy_src_fw_ov 2.283m 5.097ms 298 300 99.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 21.000s 71.317us 1000 1000 100.00
entropy_src_sec_cm 9.000s 163.821us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 21.000s 71.317us 1000 1000 100.00
entropy_src_sec_cm 9.000s 163.821us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.817m 10.023ms 299 300 99.67
V2S sec_cm_ctr_redun entropy_src_functional_errors 21.000s 71.317us 1000 1000 100.00
entropy_src_sec_cm 9.000s 163.821us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 21.000s 71.317us 1000 1000 100.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 14.000s 75.293us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 177.478us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.583m 10.061ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 27.000s 4.039ms 47 50 94.00
TOTAL 2145 2520 85.12

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 10 10 7 70.00
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
83.89 98.35 95.88 98.33 95.79 89.39 96.94 91.62 46.65

Failure Buckets

Past Results