ENTROPY_SRC Simulation Results

Thursday April 11 2024 19:07:25 UTC

GitHub Revision: 1f410ef5dc

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 77676901304510083363507443373754332549719316834151559528665885252978172929472

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 13.000s 95.081us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 111.398us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 60.159us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 17.000s 3.215ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 995.849us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 50.091us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 60.159us 20 20 100.00
entropy_src_csr_aliasing 8.000s 995.849us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 13.000s 95.081us 50 50 100.00
entropy_src_rng 4.950m 10.031ms 296 300 98.67
entropy_src_fw_ov 2.483m 5.042ms 297 300 99.00
V2 firmware_mode entropy_src_fw_ov 2.483m 5.042ms 297 300 99.00
V2 rng_mode entropy_src_rng 4.950m 10.031ms 296 300 98.67
V2 rng_max_rate entropy_src_rng_max_rate 9.367m 10.022ms 386 400 96.50
V2 health_checks entropy_src_rng 4.950m 10.031ms 296 300 98.67
V2 conditioning entropy_src_rng 4.950m 10.031ms 296 300 98.67
V2 interrupts entropy_src_rng 4.950m 10.031ms 296 300 98.67
V2 alerts entropy_src_rng 4.950m 10.031ms 296 300 98.67
entropy_src_functional_alerts 14.000s 58.642us 50 50 100.00
V2 stress_all entropy_src_stress_all 15.000s 191.578us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.917m 10.012ms 968 1000 96.80
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 28.000s 661.148us 50 50 100.00
V2 intr_test entropy_src_intr_test 4.000s 93.673us 50 50 100.00
V2 alert_test entropy_src_alert_test 9.000s 37.217us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 8.000s 560.990us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 8.000s 560.990us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 111.398us 5 5 100.00
entropy_src_csr_rw 4.000s 60.159us 20 20 100.00
entropy_src_csr_aliasing 8.000s 995.849us 5 5 100.00
entropy_src_same_csr_outstanding 6.000s 345.234us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 111.398us 5 5 100.00
entropy_src_csr_rw 4.000s 60.159us 20 20 100.00
entropy_src_csr_aliasing 8.000s 995.849us 5 5 100.00
entropy_src_same_csr_outstanding 6.000s 345.234us 20 20 100.00
V2 TOTAL 2237 2290 97.69
V2S tl_intg_err entropy_src_sec_cm 4.000s 87.037us 5 5 100.00
entropy_src_tl_intg_err 7.000s 737.581us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.950m 10.031ms 296 300 98.67
entropy_src_cfg_regwen 8.000s 24.354us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.950m 10.031ms 296 300 98.67
V2S sec_cm_config_redun entropy_src_rng 4.950m 10.031ms 296 300 98.67
V2S sec_cm_intersig_mubi entropy_src_rng 4.950m 10.031ms 296 300 98.67
entropy_src_fw_ov 2.483m 5.042ms 297 300 99.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.917m 10.012ms 968 1000 96.80
entropy_src_sec_cm 4.000s 87.037us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.917m 10.012ms 968 1000 96.80
entropy_src_sec_cm 4.000s 87.037us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.950m 10.031ms 296 300 98.67
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.917m 10.012ms 968 1000 96.80
entropy_src_sec_cm 4.000s 87.037us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.917m 10.012ms 968 1000 96.80
entropy_src_sec_cm 4.000s 87.037us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.917m 10.012ms 968 1000 96.80
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 14.000s 58.642us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 737.581us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.567m 10.024ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 19.000s 284.825us 45 50 90.00
TOTAL 2512 2570 97.74

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.26 98.17 95.37 98.33 95.84 87.90 96.88 90.46 57.40

Failure Buckets

Past Results