ENTROPY_SRC Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: dd5ad5fb77

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 51.935us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 29.654us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 19.819us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 13.000s 539.440us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 285.428us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 5.000s 68.704us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 19.819us 20 20 100.00
entropy_src_csr_aliasing 8.000s 285.428us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 4.000s 51.935us 50 50 100.00
entropy_src_rng 4.833m 10.071ms 298 300 99.33
entropy_src_fw_ov 2.283m 5.031ms 290 300 96.67
V2 firmware_mode entropy_src_fw_ov 2.283m 5.031ms 290 300 96.67
V2 rng_mode entropy_src_rng 4.833m 10.071ms 298 300 99.33
V2 rng_max_rate entropy_src_rng_max_rate 9.283m 10.089ms 390 400 97.50
V2 health_checks entropy_src_rng 4.833m 10.071ms 298 300 99.33
V2 conditioning entropy_src_rng 4.833m 10.071ms 298 300 99.33
V2 interrupts entropy_src_rng 4.833m 10.071ms 298 300 99.33
V2 alerts entropy_src_rng 4.833m 10.071ms 298 300 99.33
entropy_src_functional_alerts 4.000s 69.848us 50 50 100.00
V2 stress_all entropy_src_stress_all 12.000s 270.652us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 11.067m 10.012ms 970 1000 97.00
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 25.000s 350.918us 50 50 100.00
V2 intr_test entropy_src_intr_test 12.000s 13.163us 50 50 100.00
V2 alert_test entropy_src_alert_test 3.000s 73.602us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 14.000s 192.682us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 14.000s 192.682us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 29.654us 5 5 100.00
entropy_src_csr_rw 4.000s 19.819us 20 20 100.00
entropy_src_csr_aliasing 8.000s 285.428us 5 5 100.00
entropy_src_same_csr_outstanding 9.000s 122.716us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 29.654us 5 5 100.00
entropy_src_csr_rw 4.000s 19.819us 20 20 100.00
entropy_src_csr_aliasing 8.000s 285.428us 5 5 100.00
entropy_src_same_csr_outstanding 9.000s 122.716us 20 20 100.00
V2 TOTAL 2238 2290 97.73
V2S tl_intg_err entropy_src_sec_cm 4.000s 98.028us 5 5 100.00
entropy_src_tl_intg_err 11.000s 344.056us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.833m 10.071ms 298 300 99.33
entropy_src_cfg_regwen 4.000s 61.510us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.833m 10.071ms 298 300 99.33
V2S sec_cm_config_redun entropy_src_rng 4.833m 10.071ms 298 300 99.33
V2S sec_cm_intersig_mubi entropy_src_rng 4.833m 10.071ms 298 300 99.33
entropy_src_fw_ov 2.283m 5.031ms 290 300 96.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 11.067m 10.012ms 970 1000 97.00
entropy_src_sec_cm 4.000s 98.028us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 11.067m 10.012ms 970 1000 97.00
entropy_src_sec_cm 4.000s 98.028us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.833m 10.071ms 298 300 99.33
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 11.067m 10.012ms 970 1000 97.00
entropy_src_sec_cm 4.000s 98.028us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 11.067m 10.012ms 970 1000 97.00
entropy_src_sec_cm 4.000s 98.028us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 11.067m 10.012ms 970 1000 97.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 4.000s 69.848us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 11.000s 344.056us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.717m 10.065ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 22.000s 962.716us 42 50 84.00
TOTAL 2510 2570 97.67

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.64 98.17 95.37 98.33 95.84 88.00 96.88 90.46 58.88

Failure Buckets

Past Results