ENTROPY_SRC Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: b29ffbb03c

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 13.000s 33.300us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 183.033us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 3.000s 22.263us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 15.000s 694.822us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 7.000s 266.477us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 101.283us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 3.000s 22.263us 20 20 100.00
entropy_src_csr_aliasing 7.000s 266.477us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 13.000s 33.300us 50 50 100.00
entropy_src_rng 4.617m 10.046ms 299 300 99.67
entropy_src_fw_ov 2.333m 5.046ms 295 300 98.33
V2 firmware_mode entropy_src_fw_ov 2.333m 5.046ms 295 300 98.33
V2 rng_mode entropy_src_rng 4.617m 10.046ms 299 300 99.67
V2 rng_max_rate entropy_src_rng_max_rate 8.667m 10.018ms 383 400 95.75
V2 health_checks entropy_src_rng 4.617m 10.046ms 299 300 99.67
V2 conditioning entropy_src_rng 4.617m 10.046ms 299 300 99.67
V2 interrupts entropy_src_rng 4.617m 10.046ms 299 300 99.67
V2 alerts entropy_src_rng 4.617m 10.046ms 299 300 99.67
entropy_src_functional_alerts 14.000s 102.779us 50 50 100.00
V2 stress_all entropy_src_stress_all 9.000s 180.315us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.600m 10.013ms 971 1000 97.10
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 24.000s 333.215us 50 50 100.00
V2 intr_test entropy_src_intr_test 3.000s 13.894us 50 50 100.00
V2 alert_test entropy_src_alert_test 12.000s 34.056us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 8.000s 665.530us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 8.000s 665.530us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 183.033us 5 5 100.00
entropy_src_csr_rw 3.000s 22.263us 20 20 100.00
entropy_src_csr_aliasing 7.000s 266.477us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 230.855us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 183.033us 5 5 100.00
entropy_src_csr_rw 3.000s 22.263us 20 20 100.00
entropy_src_csr_aliasing 7.000s 266.477us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 230.855us 20 20 100.00
V2 TOTAL 2238 2290 97.73
V2S tl_intg_err entropy_src_sec_cm 4.000s 236.860us 5 5 100.00
entropy_src_tl_intg_err 8.000s 1.900ms 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.617m 10.046ms 299 300 99.67
entropy_src_cfg_regwen 13.000s 108.036us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.617m 10.046ms 299 300 99.67
V2S sec_cm_config_redun entropy_src_rng 4.617m 10.046ms 299 300 99.67
V2S sec_cm_intersig_mubi entropy_src_rng 4.617m 10.046ms 299 300 99.67
entropy_src_fw_ov 2.333m 5.046ms 295 300 98.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.600m 10.013ms 971 1000 97.10
entropy_src_sec_cm 4.000s 236.860us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.600m 10.013ms 971 1000 97.10
entropy_src_sec_cm 4.000s 236.860us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.617m 10.046ms 299 300 99.67
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.600m 10.013ms 971 1000 97.10
entropy_src_sec_cm 4.000s 236.860us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.600m 10.013ms 971 1000 97.10
entropy_src_sec_cm 4.000s 236.860us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.600m 10.013ms 971 1000 97.10
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 14.000s 102.779us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 8.000s 1.900ms 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.633m 10.067ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 31.000s 1.025ms 44 50 88.00
TOTAL 2512 2570 97.74

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.43 98.21 95.47 98.36 95.84 88.07 96.88 90.46 57.90

Failure Buckets

Past Results