ENTROPY_SRC Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: 32d52b8d41

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 8.000s 21.221us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 30.686us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 7.000s 14.957us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 14.000s 2.058ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 23.000s 219.038us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 13.000s 224.432us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 7.000s 14.957us 20 20 100.00
entropy_src_csr_aliasing 23.000s 219.038us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 8.000s 21.221us 50 50 100.00
entropy_src_rng 4.833m 10.032ms 299 300 99.67
entropy_src_fw_ov 2.400m 5.024ms 290 300 96.67
V2 firmware_mode entropy_src_fw_ov 2.400m 5.024ms 290 300 96.67
V2 rng_mode entropy_src_rng 4.833m 10.032ms 299 300 99.67
V2 rng_max_rate entropy_src_rng_max_rate 8.800m 10.017ms 387 400 96.75
V2 health_checks entropy_src_rng 4.833m 10.032ms 299 300 99.67
V2 conditioning entropy_src_rng 4.833m 10.032ms 299 300 99.67
V2 interrupts entropy_src_rng 4.833m 10.032ms 299 300 99.67
V2 alerts entropy_src_rng 4.833m 10.032ms 299 300 99.67
entropy_src_functional_alerts 5.000s 100.899us 50 50 100.00
V2 stress_all entropy_src_stress_all 10.000s 370.598us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 10.283m 10.013ms 966 1000 96.60
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 24.000s 1.315ms 50 50 100.00
V2 intr_test entropy_src_intr_test 7.000s 24.604us 50 50 100.00
V2 alert_test entropy_src_alert_test 8.000s 44.335us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 10.000s 208.480us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 10.000s 208.480us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 30.686us 5 5 100.00
entropy_src_csr_rw 7.000s 14.957us 20 20 100.00
entropy_src_csr_aliasing 23.000s 219.038us 5 5 100.00
entropy_src_same_csr_outstanding 9.000s 53.817us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 30.686us 5 5 100.00
entropy_src_csr_rw 7.000s 14.957us 20 20 100.00
entropy_src_csr_aliasing 23.000s 219.038us 5 5 100.00
entropy_src_same_csr_outstanding 9.000s 53.817us 20 20 100.00
V2 TOTAL 2232 2290 97.47
V2S tl_intg_err entropy_src_sec_cm 3.000s 88.618us 5 5 100.00
entropy_src_tl_intg_err 10.000s 435.312us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.833m 10.032ms 299 300 99.67
entropy_src_cfg_regwen 7.000s 120.064us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.833m 10.032ms 299 300 99.67
V2S sec_cm_config_redun entropy_src_rng 4.833m 10.032ms 299 300 99.67
V2S sec_cm_intersig_mubi entropy_src_rng 4.833m 10.032ms 299 300 99.67
entropy_src_fw_ov 2.400m 5.024ms 290 300 96.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 10.283m 10.013ms 966 1000 96.60
entropy_src_sec_cm 3.000s 88.618us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 10.283m 10.013ms 966 1000 96.60
entropy_src_sec_cm 3.000s 88.618us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.833m 10.032ms 299 300 99.67
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 10.283m 10.013ms 966 1000 96.60
entropy_src_sec_cm 3.000s 88.618us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 10.283m 10.013ms 966 1000 96.60
entropy_src_sec_cm 3.000s 88.618us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 10.283m 10.013ms 966 1000 96.60
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 100.899us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 10.000s 435.312us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.383m 10.037ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 23.000s 962.621us 45 50 90.00
TOTAL 2507 2570 97.55

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.77 98.17 95.37 98.33 95.84 88.12 96.88 90.46 59.36

Failure Buckets

Past Results