ENTROPY_SRC Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: 3e0219a2c5

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 5.000s 45.601us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 4.000s 45.780us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 9.000s 15.083us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 14.000s 520.626us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 7.000s 255.310us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 8.000s 56.052us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 9.000s 15.083us 20 20 100.00
entropy_src_csr_aliasing 7.000s 255.310us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 5.000s 45.601us 50 50 100.00
entropy_src_rng 5.900m 10.043ms 299 300 99.67
entropy_src_fw_ov 3.050m 5.097ms 286 300 95.33
V2 firmware_mode entropy_src_fw_ov 3.050m 5.097ms 286 300 95.33
V2 rng_mode entropy_src_rng 5.900m 10.043ms 299 300 99.67
V2 rng_max_rate entropy_src_rng_max_rate 9.983m 10.045ms 396 400 99.00
V2 health_checks entropy_src_rng 5.900m 10.043ms 299 300 99.67
V2 conditioning entropy_src_rng 5.900m 10.043ms 299 300 99.67
V2 interrupts entropy_src_rng 5.900m 10.043ms 299 300 99.67
entropy_src_intr 35.000s 2.100ms 50 50 100.00
V2 alerts entropy_src_rng 5.900m 10.043ms 299 300 99.67
entropy_src_functional_alerts 6.000s 100.868us 50 50 100.00
V2 stress_all entropy_src_stress_all 12.000s 238.561us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 10.250m 10.012ms 973 1000 97.30
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 25.000s 317.090us 50 50 100.00
V2 intr_test entropy_src_intr_test 4.000s 18.673us 50 50 100.00
V2 alert_test entropy_src_alert_test 5.000s 49.361us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 154.764us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 154.764us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 4.000s 45.780us 5 5 100.00
entropy_src_csr_rw 9.000s 15.083us 20 20 100.00
entropy_src_csr_aliasing 7.000s 255.310us 5 5 100.00
entropy_src_same_csr_outstanding 8.000s 55.962us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 4.000s 45.780us 5 5 100.00
entropy_src_csr_rw 9.000s 15.083us 20 20 100.00
entropy_src_csr_aliasing 7.000s 255.310us 5 5 100.00
entropy_src_same_csr_outstanding 8.000s 55.962us 20 20 100.00
V2 TOTAL 2294 2340 98.03
V2S tl_intg_err entropy_src_sec_cm 8.000s 2.228ms 5 5 100.00
entropy_src_tl_intg_err 7.000s 910.959us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 5.900m 10.043ms 299 300 99.67
entropy_src_cfg_regwen 4.000s 36.404us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 5.900m 10.043ms 299 300 99.67
V2S sec_cm_config_redun entropy_src_rng 5.900m 10.043ms 299 300 99.67
V2S sec_cm_intersig_mubi entropy_src_rng 5.900m 10.043ms 299 300 99.67
entropy_src_fw_ov 3.050m 5.097ms 286 300 95.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 10.250m 10.012ms 973 1000 97.30
entropy_src_sec_cm 8.000s 2.228ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 10.250m 10.012ms 973 1000 97.30
entropy_src_sec_cm 8.000s 2.228ms 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 5.900m 10.043ms 299 300 99.67
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 10.250m 10.012ms 973 1000 97.30
entropy_src_sec_cm 8.000s 2.228ms 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 10.250m 10.012ms 973 1000 97.30
entropy_src_sec_cm 8.000s 2.228ms 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 10.250m 10.012ms 973 1000 97.30
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 6.000s 100.868us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 910.959us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.950m 10.044ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
TOTAL 2524 2570 98.21

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 8 66.67
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.18 98.19 95.43 98.36 95.79 96.71 96.88 90.48 96.08

Failure Buckets

Past Results