ENTROPY_SRC Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: 0bfa990ddc

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 13.000s 30.423us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 4.000s 39.763us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 25.122us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 15.000s 794.647us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 7.000s 216.732us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 9.000s 28.829us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 25.122us 20 20 100.00
entropy_src_csr_aliasing 7.000s 216.732us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 13.000s 30.423us 50 50 100.00
entropy_src_rng 5.233m 10.030ms 298 300 99.33
entropy_src_fw_ov 2.900m 5.013ms 285 300 95.00
V2 firmware_mode entropy_src_fw_ov 2.900m 5.013ms 285 300 95.00
V2 rng_mode entropy_src_rng 5.233m 10.030ms 298 300 99.33
V2 rng_max_rate entropy_src_rng_max_rate 9.583m 10.071ms 391 400 97.75
V2 health_checks entropy_src_rng 5.233m 10.030ms 298 300 99.33
V2 conditioning entropy_src_rng 5.233m 10.030ms 298 300 99.33
V2 interrupts entropy_src_rng 5.233m 10.030ms 298 300 99.33
entropy_src_intr 23.000s 1.990ms 50 50 100.00
V2 alerts entropy_src_rng 5.233m 10.030ms 298 300 99.33
entropy_src_functional_alerts 9.000s 74.607us 50 50 100.00
V2 stress_all entropy_src_stress_all 11.000s 1.852ms 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.750m 10.012ms 965 1000 96.50
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 23.000s 646.447us 49 50 98.00
V2 intr_test entropy_src_intr_test 4.000s 32.824us 50 50 100.00
V2 alert_test entropy_src_alert_test 7.000s 155.566us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 151.887us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 151.887us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 4.000s 39.763us 5 5 100.00
entropy_src_csr_rw 4.000s 25.122us 20 20 100.00
entropy_src_csr_aliasing 7.000s 216.732us 5 5 100.00
entropy_src_same_csr_outstanding 7.000s 89.689us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 4.000s 39.763us 5 5 100.00
entropy_src_csr_rw 4.000s 25.122us 20 20 100.00
entropy_src_csr_aliasing 7.000s 216.732us 5 5 100.00
entropy_src_same_csr_outstanding 7.000s 89.689us 20 20 100.00
V2 TOTAL 2278 2340 97.35
V2S tl_intg_err entropy_src_sec_cm 4.000s 57.451us 5 5 100.00
entropy_src_tl_intg_err 7.000s 979.964us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 5.233m 10.030ms 298 300 99.33
entropy_src_cfg_regwen 8.000s 15.425us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 5.233m 10.030ms 298 300 99.33
V2S sec_cm_config_redun entropy_src_rng 5.233m 10.030ms 298 300 99.33
V2S sec_cm_intersig_mubi entropy_src_rng 5.233m 10.030ms 298 300 99.33
entropy_src_fw_ov 2.900m 5.013ms 285 300 95.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.750m 10.012ms 965 1000 96.50
entropy_src_sec_cm 4.000s 57.451us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.750m 10.012ms 965 1000 96.50
entropy_src_sec_cm 4.000s 57.451us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 5.233m 10.030ms 298 300 99.33
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.750m 10.012ms 965 1000 96.50
entropy_src_sec_cm 4.000s 57.451us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.750m 10.012ms 965 1000 96.50
entropy_src_sec_cm 4.000s 57.451us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.750m 10.012ms 965 1000 96.50
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 9.000s 74.607us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 979.964us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 5.067m 10.080ms 49 50 98.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 49 50 98.00
TOTAL 2507 2570 97.55

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 7 58.33
V2S 3 3 3 100.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.14 98.15 95.32 98.36 95.79 96.62 96.88 90.48 95.93

Failure Buckets

Past Results